ADSP-21266SKBCZ-2C Analog Devices, ADSP-21266SKBCZ-2C Datasheet

ADSP-21266SKBCZ-2C

Manufacturer Part Number

ADSP-21266SKBCZ-2C

Description

Manufacturer

Analog Devices

Datasheets

1.ADSP-21266SKSTZ-2B.pdf (48 pages)

2.ADSP-21266SKBCZ-2C.pdf (44 pages)

Specifications of ADSP-21266SKBCZ-2C

Date_code

07+

Current page: 1 of 48
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SUMMARY

High performance 32-bit/40-bit floating-point processor

Code compatibility—at assembly level, uses the same

Processes high performance audio while enabling low

Audio decoders and postprocessor algorithms support

Various multichannel surround sound decoders are con

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

optimized for high performance audio processing

instruction set as other SHARC DSPs

system costs

nonvolatile memory that can be configured to contain a

combination of PCM 96 kHz, Dolby

Surround EX

DTS

PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and

DTS Neo:6

tained in ROM. For configurations of decoder algorithms,

see

Table 3 on Page

96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA

, DTS-ES

PROCESSING

ELEMENT

Discrete 6.1, DTS-ES Matrix 6.1,

(PEX)

8 � 4 � 32

DAG1

JTAG TEST & EMULATION

PRO CESSING

8 � 4 � 32

ELEMENT

DAG2

(PEY)

CORE PROCESSOR

Digital, Dolby Digital

PM ADDRESS BUS

DM ADDRESS BUS

PX REGI STER

TIMER

SEQ UENCER

PROG RAM

Figure 1. Functional Block Diagram

INSTRUCTION

32 � 48-BIT

CACHE

ADSP-21261/ADSP-21262/ADSP-21266

DM DATA BUS

PM DATA BUS

RO UTI NG

SIGNAL

UNIT

DIGITAL AUDIO INTERFACE

ACQUISITION PORT

ADDR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

FAX: 781.461.3113

SPI PORT (1)

SERIAL PORTS (6)

PARALLEL DATA

PRECISION CLOCK

Single-instruction multiple-data (SIMD) computational archi

High bandwidth I/O—a parallel port, an SPI port, 6 serial

DAI incorporates two precision clock generators (PCGs), an

On-chip memory—up to 2M bits on-chip SRAM and a dedi

The ADSP-2126x processors are available with a 150 MHz or a

DATA PORTS (8)

DMA CONTRO LLER

GENERATORS (2)

PERIPHERAL

TIMERS (3)

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

ports, a digital audio interface (DAI), and JTAG

input data port (IDP) that includes a parallel data acquisi

tion port (PDAP), and 3 programmable timers, all under

software control by the signal routing unit (SRU)

cated 4M bits on-chip mask-programmable ROM

200 MHz core instruction rate. For complete ordering

information, see

2 2 C HA N N ELS

INPUT

DUAL PORTED MEMORY

DATA

SRAM

1M BIT

BLOCK 0

I/O PROCESSOR

ROM

2M BIT

(MEMORY MAPPED)

IOD

(32)

DATA BUFFERS

Embedded Processor

Ordering Guide on Page

REGISTERS

CO NTROL,

STATUS,

IOP

IOA

(19)

DUAL PORTED MEMORY

SRAM

1M BIT

BLO CK 1

GPIO FLAGS/

IRQ /TIMEXP

D A TA BU S / GPIO

CON TR OL/GPIO

ADDR

PARALLEL

AD D R ES S/

PORT

ROM

2M BIT

DATA

47.

www.analog.com

SHARC

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