IDT74ALVCH162373PVG8 IDT, Integrated Device Technology Inc, IDT74ALVCH162373PVG8 Datasheet

IDT74ALVCH162373PVG8

Manufacturer Part Number

IDT74ALVCH162373PVG8

Description

IC XPARENT LATCH 16BIT D 48-SSOP

Manufacturer

IDT, Integrated Device Technology Inc

Series

74ALVCHr

Datasheet

1.IDT74ALVCH162373PAG.pdf (6 pages)

Specifications of IDT74ALVCH162373PVG8

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2.3 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1.5ns

Current - Output High, Low

12mA, 12mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-SSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74ALVCH162373PVG8

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FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in SSOP and TSSOP packages

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

IDT74ALVCH162373

3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

machine model (C = 200pF, R = 0)

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

= 2.5V ± 0.2V

SK(o)

(Output Skew) < 250ps

TO 7 OTHER CHANNELS

3.3V CMOS 16-BIT TRANS-

PARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

AND BUS-HOLD

DESCRIPTION:

technology. The ALVCH162373 is particularly suitable for imple-menting buffer

registers, I/O ports, bidirectional bus drivers, and working registers. This device

can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE)

input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the levels set up at the D inputs.

a normal logic state (high or low logic levels) or a high-impedance state. In the

high-impedance state, the outputs neither load nor drive the bus lines signifi-

cantly. The high-impedance state and the increased drive provide the capability

to drive bus lines without need for interface or pullup components. OE does not

affect internal operations of the latch. Old data can be retained or new data can

be enetered while the outputs are in the high-impedance state.

will significantly reduce line noise when used with light loads. This driver has

been designed to drive ±12mA at the designated threshold levels.

whenever the input goes to a high impedance. This prevents floating inputs and

eliminates the need for pull-up/down resistor.

This 16-bit transparent D-type latch is built using advanced dual metal CMOS

The ALVCH162373 has series resistors in the device output structure which

The ALVCH162373 has “bus-hold” which retains the inputs’ last state

A buffered output-enable (OE) can be used to place the eight outputs in either

TO 7 OTHER CHANNELS

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH162373

JULY 2009

DSC-4575/6

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IDT74ALVCH162373PVG8 Summary of contents

Page 1

IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, ...

Page 2

IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS PIN CONFIGURATION GND ...

Page 3

IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input ...

Page 4

IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in ...

Page 5

IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 ...

Page 6

IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS ORDERING INFORMATION ALVC Temp. Range Bus-Hold Family Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXX Package PVG Shrink Small Outline ...

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