SY100S350JC Micrel Inc, SY100S350JC Datasheet

IC HEX D-LATCH 28-PLCC

SY100S350JC

Manufacturer Part Number
SY100S350JC
Description
IC HEX D-LATCH 28-PLCC
Manufacturer
Micrel Inc
Series
100Sr
Datasheet

Specifications of SY100S350JC

Logic Type
D-Type Transparent Latch
Circuit
6:6
Output Type
Differential
Voltage - Supply
4.2 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
300ps
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output High, Low
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SY100S350JC
Manufacturer:
Micrel Inc
Quantity:
10 000
Micrel, Inc.
M9999-042307
hbwhelp@micrel.com or (408) 955-1690
D
E
MR
Q
Q
V
V
FEATURES
PIN NAMES
Max. transparent propagation delay of 900ps
Min. Master Reset and Enable pulse widths of 100ps
I
Industry standard 100K ECL levels
Extended supply voltage option:
V
Voltage and temperature compensation for improved
noise immunity
Internal 75k input pull-down resistors
More than 40% faster than Fairchild
Approximately 30% lower power than Fairchild
Function and pinout compatible with Fairchild F100K
Available in 28-pin PLCC package
EE
a
EES
CCA
0
0
0
EE
, E
— D
— Q
— Q
Pin
min. of –98mA
b
= –4.2V to –5.5V
5
5
5
Data Inputs
Common Enable Inputs (Active LOW)
Asynchronous Master Reset Input
Data Outputs
Complementary Data Outputs
V
V
EE
CCO
Substrate
for ECL Outputs
Function
HEX D-LATCH
1
both true and complement outputs, and is performance
compatible for use with high-performance ECL systems.
When both enable signals (E
the latches are transparent and the input signals( D
appear at the outputs (Q
either or both of the enable signals are at a logic HIGH, then
the latches store the last valid data present on its inputs
before E
(MR) overrides all other input signals and takes the outputs
to a logic LOW state. All inputs have 75k
resistors.
DESCRIPTION
BLOCK DIAGRAM
The SY100S350 offers six high-speed D-Latches with
a
MR
or E
D
D
D
D
D
D
E
E
5
b
a
4
3
2
1
0
b
went to a logic HIGH. The Master Reset
0
–Q
5
a
) after a propagation delay. If
D
D
D
D
D
D
E
E
E
E
E
E
and E
R
R
R
R
R
R
b
) are at a logic LOW,
Rev.: I
Issue Date: April 2007
SY100S350
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
5
5
4
4
3
3
2
2
1
1
0
0
SY100S350
Amendment: /0
pull-down
0
–D
5
)

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SY100S350JC Summary of contents

Page 1

Micrel, Inc. FEATURES Max. transparent propagation delay of 900ps Min. Master Reset and Enable pulse widths of 100ps I min. of –98mA EE Industry standard 100K ECL levels Extended supply voltage option –4.2V to –5.5V EE Voltage and ...

Page 2

... Tape and Reel. 2. Pb-Free package is recommended for new designs. Outputs (2) (2) L Latched Latched (2) (2) L Latched Latched SY100S350 Package Range Marking SY100S350JC SY100S350JC SY100S350JZ with Pb-Free bar-line indicator SY100S350JZ with Pb-Free bar-line indicator Operating Mode Latch Asynchronous Lead Finish Sn-Pb Sn-Pb Matte-Sn Matte-Sn ...

Page 3

Micrel, Inc. DC ELECTRICAL CHARACTERISTICS V = –4.2V to –5.5V unless otherwise specified Symbol Parameter I Input HIGH Current Ea Power Supply Current EE AC ELECTRICAL CHARACTERISTICS V = –4.2V to –5.5V unless ...

Page 4

Micrel, Inc. TIMING DIAGRAMS DATA ENABLE TRANSPARENT OUTPUT Note –4.2V to –5.5V unless otherwise specified DATA ENABLE PHL PLH OUTPUT ENABLE Notes the minimum time before the transition of the ...

Page 5

Micrel, Inc. 28-PIN PLCC (J28-1) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is ...

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