74F164APC Fairchild Semiconductor, 74F164APC Datasheet - Page 2

• Manufacturer Part Number: 74F164APC
• Description: IC REGISTER SER/PAR I/O 14DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F164APC

• Logic Type: Shift Register
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Serial to Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connection Diagrams
Unit Loading Fan Out
Functional Description
The ’F164A is an edge-triggered 8-bit shift register with seri-
al data entry and an output from each of the eight stages
Data is entered serially through one of two inputs (A or B)
either of these inputs can be used as an active HIGH En-
able for data entry through the other input An unused input
must be tied HIGH
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q
AND of the two data inputs (A
rising clock edge A LOW level on the Master Reset (MR)
input overrides all other inputs and clears the register asyn-
chronously forcing all Q outputs LOW
Logic Diagram
Pin Names
A B
CP
MR
Q
0
– Q
7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
DIP SOIC and Flatpak
Pin Assignment for
Description

B) that existed before the
0
TL F 10613 – 2
the logical
HIGH LOW
50 33 3
1 0 1 0
1 0 1 0
1 0 1 0
U L
2
H(h)
L(l)
X
q
one setup time prior to the LOW-to-HIGH clock transition
n
e
Reset (Clear)
Shift
e
54F 74F
e
Operating
e
Immaterial
Lower case letters indicate the state of the referenced input or output
LOW Voltage Levels
Mode
HIGH Voltage Levels
20 mA
20 mA
20 mA
Output I
b
Input I
1 mA 20 mA
b
b
b
IH
OH
0 6 mA
0 6 mA
0 6 mA
I
IL
I
Mode Select Table
OL
MR
Pin Assignment
H
H
H
H
L
for LCC
Inputs
A
X
h
h
l
l
B
X
h
h
l
l
Q
H
L
L
L
L
0
Outputs
TL F 10613 – 3
TL F 10613 – 5
Q
q
q
q
q
1
0
0
0
0
L-L
– Q
– q
– q
– q
– q
6
6
6
6
7