HMS81008E Hynix Semiconductor, HMS81008E Datasheet
HMS81008E
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HMS81008E Summary of contents
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... HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS HMS81004E HMS81008E HMS81016E HMS81024E HMS81032E User’s Manual (Ver. 1.00) ...
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... Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor way responsible for any violations of patents or other rights of the third party generated by the use of this manual. ...
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Table of Contents 1. OVERVIEW ...........................................1 Description .........................................................1 Features .............................................................1 Development Tools ............................................ 2 2. BLOCK DIAGRAM ..............................3 3. PIN ASSIGNMENT (Top View) ........... 4 4. PACKAGE DIMENSION .......................5 5. PIN FUNCTION .....................................8 6. PORT STRUCTURES .........................10 7. ELECTRICAL CHARACTERISTICS ...
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... UR applications.The HMS81004E/08E/16E/24E/32E provides the fol- lowing standard features: 4/8/16/24/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the HMS81004E/08E/16E/24E/32E supports power saving modes to reduce power consumption. Device Name HMS81004E HMS81008E HMS81016E HMS81024E HMS81032E HMS81020TL HMS81032TL 1 ...
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HMS81004E/08E/16E/24E/32E 1.3 Development Tools The HMS81004E/08E/16E/24E/32E are supported by a full-fea- tured macro assembler, an in-circuit emulator CHOICE-Dr. and OTP programmers. Macro assembler operates under the MS- TM Windows 95/98 /NT4/W2000. Please contact sales part of HYNIX 2 - MS- ...
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BLOCK DIAGRAM Watchdog REMOUT R17/T0 Timer R16/T1 R15/T2 R14/EC R12/INT2 Interrupt R11/INT1 Key Scan R00~R07 R10~R17 Generation Block TEST Clock Gen. RESET System XIN Control XOUT VDD JUNE 2001 Ver 1.00 G8MC Core Timer RAM (448byte) ROM (32kbyte) INT. ...
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HMS81004E/08E/16E/24E/32E 3. PIN ASSIGNMENT (Top View) R13 1 R14 28 R12 2 R15 27 R11 3 R16 26 R10 4 R17 25 VDD 5 REMOUT 24 XOUT 6 RESET 23 XIN 7 TEST 22 28PIN R00 8 R07 21 R01 ...
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PACKAGE DIMENSION 20 SOP 0.020 0.013 20 PDIP MAX 0.180 0.021 0.015 JUNE 2001 Ver 1.00 0.512 0.495 0.050 BSC 1.043 1.015 0.100 BSC 0.065 0.050 HMS81004E/08E/16E/24E/32E UNIT: INCH MAX MIN 0 ~ 8° 0.042 0.016 0.300 BSC 0.270 ...
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HMS81004E/08E/16E/24E/32E 24 SOP 0.020 0.013 24 SKDIP MAX 0.180 0.021 0.015 6 0.614 0.598 0.050 BSC 1.265 1.160 0.100 BSC 0.065 0.045 UNIT: INCH MAX MIN 0 ~ 8° 0.042 0.016 0.300 BSC 0.300 0.250 MIN 0.015 0 ~ 15° ...
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SOP 0.020 0.013 28 SKDIP MAX 0.180 0.021 0.015 JUNE 2001 Ver 1.00 0.713 0.697 0.050 BSC 1.375 1.355 0.100 BSC 0.055 0.045 HMS81004E/08E/16E/24E/32E UNIT: INCH MAX MIN 0 ~ 8° 0.042 0.016 0.300 BSC 0.300 0.275 MIN 0.015 ...
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HMS81004E/08E/16E/24E/32E 5. PIN FUNCTION V : Supply voltage Circuit ground. SS TEST: Used for shipping inspection of the IC. For normal operation, it should be connected to V RESET: Reset the MCU Input to the ...
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INPUT/ PIN NAME OUTPUT R00 I/O R01 I/O R02 I/O R03 I/O R04 I/O R05 I/O R06 I/O R07 I/O R10 I/O R11/INT1 I/O R12/INT2 I/O R13 I/O R14/EC I/O R15/T2 I/O R16/T1 I/O R17/T0 I/O R20 I/O R21 I/O ...
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HMS81004E/08E/16E/24E/32E 6. PORT STRUCTURES R0[0:7] OTP : connected MASK : option (default connected) LVD Circuit Pull up Reg. Open Drain Reg. Data Reg. Dir. Reg. MUX Rd Key Scan MUX Input KS_EN Standby Release Level Control Register R10, R13 OTP ...
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R15/T2, R16/T1, R17/T0 OTP : connected MASK : option (default connected) LVD Circuit Pull up Reg. Open Drain Reg. Data Reg. Function Sele- ction Reg. Dir R eg. MUX Rd to R15...T2 MUX to R16...T1 to R17...T0 Key Scan MUX ...
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HMS81004E/08E/16E/24E/32E 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +5.0 V Input Voltage .....................................-0 Output Voltage ...................................-0 Operating Temperature........................................ 0~70 C Storage Temperature ...................................... -65~150 C Power Dissipation................................................700 mA 7.2 Recommended Operating ...
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Parameter Symbol High Level I OH output current Low Level I OL output cruuent Input pull-up current DD1 I DD2 I SLP1 Power Supply Current I SLP2 I STP1 I STP2 RAM retention V RET supply voltage ...
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HMS81004E/08E/16E/24E/32E 7.5 REMOUT Port Iol Characteristics Graph (typical process & room temperature) . Iol(mA 0.5 7.6 AC Characteristics (T =0~+ =2.0~3. Parameter External clock input cycle ...
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X IN INT1 INT2 RESET EC JUNE 2001 Ver 1. CPH RCP FCP 0. RSTL t t ECH ECL Figure 7-3 Timing Diagram HMS81004E/08E/16E/24E/32E t CPL V -0.5V DD ...
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HMS81004E/08E/16E/24E/32E 8. MEMORY ORGANIZATION The HMS81004E/08E/16E/24E/32E has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can 8.1 Registers This device has six registers that are the ...
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Stack Address ( 100 ~ 1FF Hardware fixed At execution of a CALL/TCALL/PCALL 01FC 01FD Push 01FE PCL down PCH 01FF SP before 01FF execution SP after 01FD execution 01FC 01FD 01FE 01FF ...
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HMS81004E/08E/16E/24E/32E [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g=1, page is addressed by ...
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Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 4/8/16/24/32K bytes pro- gram memory space only physically implemented. Ac- cessing a location above FFFF H to 0000 . H Figure ...
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HMS81004E/08E/16E/24E/32E Address PCALL Area Memory 0FF00 H 0FFBF H PCALL rel 4F35 PCALL 35H 0FF00H 0FF35H NEXT 0FFFFH 20 PCALL Area (192 Bytes) Figure 8-7 PCALL and TCALL Memory Area TCALL Address Program ...
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Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED DW NOT_USED DW NOT_USED DW BIT_INT DW WDT_INT DW NOT_USED DW NOT_USED DW TMR2_INT DW TMR1_INT DW TMR0_INT DW NOT_USED DW INT2 DW INT1 ...
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HMS81004E/08E/16E/24E/32E 8.3 Data Memory Figure 8-8 shows the internal Data Memory space availa- ble. Data Memory is divided into 3 groups, a user RAM, control registers, Stack. 0000H RAM (192 Bytes) 00BFH 00C0H CONTROL REGISTERS 00FFH 0100H RAM (STACK) (256 ...
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List for Control Registers Address 00C0h PORT R0 DATA REG. 00C1h PORT R0 DATA DIRECTION REG. 00C2h PORT R1 DATA REG. 00C3h PORT R1 DATA DIRECTION REG. 00C4h PORT R2 DATA REG. 00C5h PORT R2 DATA DIRECTION REG. 00C6h ...
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HMS81004E/08E/16E/24E/32E 00DFh PORT R2 OPEN DRAIN ASSIGN REG. 00E0h Reserved 00E1h Reserved 00E2h Reserved 00E3h Reserved 00E4h PORT R0 OPEN DRAIN ASSIGN REG. 00E5h Reserved 00E6h Reserved 00E7h Reserved 00E8h Reserved 00E9h Reserved 00EAh Reserved 00EBh Reserved 00ECh Reserved 00EDh ...
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Addressing Mode The HMS81004E/08E/16E/24E/32E uses six addressing modes; • Register addressing • Immediate addressing • Direct page addressing • Absolute addressing • Indexed addressing • Register-indirect addressing (1) Register Addressing Register addressing accesses the and ...
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HMS81004E/08E/16E/24E/32E 0735F0 ADC !0F035H 0F035 data 0F100 0F101 H 0F102 ROM[0F035H] A+data+C A address: 0F035 JUNE 2001 Ver 1.00 ...
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135 less of G-flag and RPR. 983501 INC !0135H 135 data 0F100 98 H 0F101 35 H ...
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HMS81004E/08E/16E/24E/32E Y indexed direct page (8 bit offset) This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead ...
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Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10 H 1725 ...
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HMS81004E/08E/16E/24E/32E 9. I/O PORTS The HMS81004E/08E/16E/24E/32E has 24 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O). Pull-up resistor of each port can be selectable by program. Each port contains data direction register which controls I/ O ...
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R1 Data Register (R/W) R17 R16 R15 R14 R13 R12 R11 R10 R1 R1 Direction Register (W) R1DD R1 Pull-up Control Register (W) R1PC R1 Open drain Assign Register (W) P1ODC R1 Port Mode Register (W) PMR1 (1) R1 I/O ...
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HMS81004E/08E/16E/24E/32E pull-up is automatically disabled, if corresponding port is selected as output. 9.3 R2 Port 8-bit CMOS bidirectional I/O port (address 0C4 ). Each I/O pin can independently used as an input output through ...
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CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock. Prescaler consist ...
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HMS81004E/08E/16E/24E/32E 10.1 Oscillation Circuit Oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. Figure 10-2 shows circuit diagrams using a crystal (or ceramic) oscillator. As shown in the diagram, oscillation circuits can be ...
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Frequency Resonator Maker CQ CQ 2.00MHz MURATA MURATA MURATA CQ CQ MURATA MURATA 4.00MHz MURATA TDK TDK CORETECK CORETECK JUNE 2001 Ver 1.00 Part Name ZTT2.00 ZTA2.00 CSTLS2M00G56-B0 CSTCC2.00MG0H6 CSTCC2M00G56-R0 ZTT4.00 ZTA4.00 CSTS0400MG06 CSTLS4M00G56-B0 CSTCR4M00G55-R0 FCR4.0MC5 FCR4.0MSC5 CRT4.00MS CRM4.00MS Table ...
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HMS81004E/08E/16E/24E/32E 11. BASIC INTERVAL TIMER The HMS81004E/08E/16E/24E/32E has one 8-bit Basic Interval Timer that is free-run and can not stop. Block dia- gram is shown in Figure 11-1 . The Basic Interval Timer generates the time base for Standby release ...
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CKCTLR - - WDTON Caution: Both register are in same address, when write CKCTLR, when read BITR BITR 8-BIT FREE-RUN BINARY COUNTER BTS[2:0] 000 ...
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HMS81004E/08E/16E/24E/32E 12. WATCH DOG TIMER Watch Dog Timer (WDT) consists of 6-bit binary counter, 6-bit comparator, and Watch Dog Timer Register (WDTR).Watch Dog Timer can be used 6-bit general Tim specific Watch dog timer by setting bit5 (WDTON) ...
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Timer0, Timer1, Timer2 (1) Timer Operation Mode Timer consists of 16bit binary counter Timer0 (T0), 8bit binary Timer1 (T1), Timer2 (T2), Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and con- trol circuit. Timer Data Register Consists ...
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HMS81004E/08E/16E/24E/32E T0HMD T0LMD from EC/R14 Timer0 (16bit) Edge Selection from INT2/R12 (Capture Signal) Timer 01 mode register TM01 REMOUT Port Output Selection (TOUT Logic or TOUTB) 0: Bit(TOUTB) Output Through REMOUT 1: TOUT Logic Output Through REMOUT REMOUT Port Bit ...
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IEDS[5: INT2/R12 PIN cto r EC PIN ...
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HMS81004E/08E/16E/24E/32E T1ST ...
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T2ST ...
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HMS81004E/08E/16E/24E/32E 2) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register T0 Data Register Value T0 Value 0 Timer 0 (IFT0) Interrupt For Timer0, the internal clock (PS) and ...
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TDR Timer 0 (IFT0) Interrupt Occur interrupt T0ST Start & Stop T0CN Control count INT2 JUNE 2001 Ver 1.00 disable clear & start stop T0ST = 1 T0ST = 0 Figure 13-6 Start/Stop Operation of Timer0 ...
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HMS81004E/08E/16E/24E/32E 3) Single/Modulo-N Mode Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM01) output level of Timer Output port. If initial level is “L”, Low-Data Register value of Timer Data Register is transferred to comparator and T0OUT (T1OUT ...
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INTERRUPTS The HMS81004E/08E/16E/24E/32E interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt en- able register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 8 interrupt sources are provided. The ...
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HMS81004E/08E/16E/24E/32E 14.1 Interrupt priority and sources Each interrupt vector is independent and has its own pri- ority. Software interrupt (BRK) is also available. Interrupt 14.2 Interrupt control register I flag of PSW is a interrupt mask enable flag. When I ...
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IENL MSB Watchdog timer R/W IENH KSCNE MSB Key scan External interrupt 1 External interrupt IRQL MSB Watchdog timer R/W IRQH KSCNR MSB Key scan External interrupt 1 External interrupt 2 14.3 Interrupt accept mode The ...
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HMS81004E/08E/16E/24E/32E l Interrupt mode register IMOD Priority 00: Fixed by hardware 01: Changeable by IP3~IP0 1x: Interrupt is inhibited Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0 14.4 Interrupt Sequence An interrupt request is held until the interrupt is ...
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System clock Instruction Fetch Address Bus Data Bus Internal Read Internal Write V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt ...
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HMS81004E/08E/16E/24E/32E 14.5 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK inter- rupt ...
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Ext. Int. Edge Selection reg. IEDS IED2* 01: Falling Edge Selection 10: Rising Edge Selection 11: Both Edsg Selection Response Time The INT1 ~ INT2 edge are latched into IFINT1 ~ IFINT2 at every machine cycle. The values are not ...
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HMS81004E/08E/16E/24E/32E Standby release level control register (SRLC) can select the key scan input level “L” or “H” for standby release by each bit pin (R0, R1). Standby release level control register SMRR0 ...
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STANDBY FUNCTION 15.1 Sleep Mode SLEEP mode can be entered by setting the bit of SLEEP mode register (SLPM). In the mode, CPU clock stops but oscillator keeps running. B.I.T and a part of peripheral hardware execute, but prescalerís ...
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HMS81004E/08E/16E/24E/32E OSC Circuit STOP 15.3 STANDBY MODE RELEASE Release of STANDBY mode is executed by RESET input and Interrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET ...
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Release Factor RESETB By RESETB Pin=Low level, Standby mode is releas and system is initialized Standby mode is released by low input of selected pin by key scan Input(SMRR0,SMRR1). KSCN(Key Input) In case of interrupt mask enable flag= “0”, program ...
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HMS81004E/08E/16E/24E/32E 15.4 RELEASE OPERATION OF STANDBY MODE After standby mode is released, the operation begins ac- cording to content of related interrupt register just before . (1) Interrupt Enable Flag(I) of PSW = “0” Release by only interrupt which interrupt ...
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Internal circuit Oscillator Internal CPU Register Prescaler Basic Interval Timer Watch-dog Timer Address Bus,Data Bus JUNE 2001 Ver 1.00 SLEEP mode Active Stop Retained RAM Retained I/O port Retained Active PS10 selected:Active Others: Stop Stop Timer Stop Retained Table 15-3 ...
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HMS81004E/08E/16E/24E/32E 16. RESET FUNCTION 16.1 EXTERNAL RESET The RESET pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uF capacitor for 16.2 POWER ON ...
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RESET 0.1uF GND OSC Circuit Note: When Power On Reset, oscillator stabilization time doesn`t include OSC. Start time. VDD OSC. Start Time JUNE 2001 Ver 1.00 VDD GND Clear PS10 Prescaler Figure 16-2 Block Diagram of Power On Reset Circuit ...
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HMS81004E/08E/16E/24E/32E Oscillator (X pin) IN RESET ADDRESS BUS DATA BUS ADL and ADH are start addresses of interrupt service routine as vector contents. 16.3 Low Voltage Detection Mode (1) Low voltage detection condition An on board voltage comparator checks that ...
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SRAM BACK-UP after Low Voltage Detection. VDD 3V 2V(Min.) 1.7V(typ.20 C) 0.7V(Vret) 0V User removes batteries JUNE 2001 Ver 1.00 about hours depend on Vdd-GND Capacitor SRAM Data Backup Low Voltage detetion point Figure 16-6 Oscillator stabiliaztion diagram Interrupt ...
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HMS81004E/08E/16E/24E/32E (5) S/W flow chart example after Reset using SRAM Back-up Figure 16-7 S/W flow chart example after Reset using SRAM Back-up 64 RESET Stack Pointer initialize Check the SRAM value (RAM Pattern, Checksum) N SRAM DATA VALID? Y Use ...
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APPENDIX ...
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A. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET HMS810 Customer should write inside thick line box. 1. Customer Information Company Name Application YYYY Order Date Tel: Fax: Name&Signature: 3. Inclusion of pull-up resistor in Low Volatage Detection mode Port ...
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B. INSTRUCTION B.1 Terminology List Terminology PSW #imm dp !abs [ ] { } { }+ .bit A.bit dp.bit M.bit rel upage JUNE 2001 Ver 1.00 Accumulator X ...
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APPENDIX B.2 Instruction Map 00000 00001 00010 00011 LOW HIGH SET1 BBS BBS 000 - dp.bit A.bit,rel dp.bit,rel 001 CLRC 010 CLRG 011 DI 100 CLRV 101 SETC 110 SETG 111 EI 10000 10001 10010 10011 ...
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B.3 Instruction Set Arithmetic / Logic Operation Op No. Mnemonic Code 1 ADC #imm 04 2 ADC ADC ADC !abs 07 5 ADC !abs + ADC [ dp + ...
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APPENDIX Op No. Mnemonic Code 44 DIV 9B 45 EOR #imm A4 46 EOR EOR EOR !abs A7 49 EOR !abs + EOR [ ...
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Register / Memory Operation Op No. Mnemonic Code 1 LDA #imm C4 2 LDA LDA LDA !abs C7 5 LDA !abs + LDA [ ...
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APPENDIX 16-BIT operation Op No. Mnemonic Code 1 ADDW CMPW DECW INCW LDYA STYA SUBW dp 3D Bit Manipulation Op No. Mnemonic ...
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Branch / Jump Operation Op No. Mnemonic Code 1 BBC A.bit,rel y2 2 BBC dp.bit,rel y3 3 BBS A.bit,rel x2 4 BBS dp.bit,rel x3 5 BCC rel 50 6 BCS rel D0 7 BEQ rel F0 8 BMI rel 90 ...
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APPENDIX Control Operation & Etc. Op No. Mnemonic Code 1 BRK NOP FF 5 POP POP POP POP PSW 6D 9 PUSH A ...