ISPGDXTMFAMILY LATTICE [Lattice Semiconductor], ISPGDXTMFAMILY Datasheet
ISPGDXTMFAMILY
Related parts for ISPGDXTMFAMILY
ISPGDXTMFAMILY Summary of contents
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Features • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options 160 Programmable I/O Pins — “Any Input to Any Output” Routing — Fixed ...
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Description (Continued) ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access ...
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Architecture The ispGDX architecture is different from traditional PLD architectures, in keeping with its unique application fo- cus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are ...
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Applications The ispGDX family architecture has been developed to deliver an in-system programmable signal routing solu- tion with high speed and high flexibility. The devices are targeted for three similar but distinct classes of end- system applications: Programmable, Random Signal ...
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Applications (Cont.) Figure 3. Address Demultiplex/Data Buffering XCVR I/OA I/OB OEA OEB Address Latch D Q CLK Figure 4. Data Bus Byte Swapper XCVR D0-7 I/OA I/OB OEA OEB XCVR D8-15 I/OA I/OB OEA OEB Figure 5. Four-Port Memory Interface ...
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Absolute Maximum Ratings Supply Voltage V ................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A 160 Active High B ...
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External Timing Parameters TEST 1 PARAMETER # COND Data Propagation Delay from any I/O pin to any I/O pin t sel A 2 Data Propagation Delay from MUXsel Inputs to any Output f – 3 Clock ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 21 Input Buffer Delay io GRP t 22 GRP Delay grp MUX t 23 I/O Cell MUX A/B/C/D Data Delay muxd t 24 I/O Cell MUX A/B/C/D Data Select muxs Register t ...
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Switching Waveforms VALID INPUT MUXSEL (I/O INPUT) t sel DATA (I/O INPUT) VALID INPUT t pd COMBINATORIAL I/O OUTPUT Combinatorial Output OE (I/O INPUT) t dis COMBINATORIAL I/O OUTPUT I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ...
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Development System The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-to- use Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool ...
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The GDF File The GDF file is a simple text description of the design function, device and pin parameters. The file has four parts: device selection, set and constant statements, a pin section and a connection section. A sample file ...
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Download .jed - JEDEC Device Programming File Third-Party Timing Simulation The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. In-System ...
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Boundary Scan / ISP Programming and Test Options The ispGDX devices provide IEEE1149.1a test capabil- ity and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface. In addition, ispGDX devices can be programmed via the Lattice ISP ...
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Boundary Scan / ISP Programming and Test Options (Continued) The ispGDX devices are identified either by the 32-bit JTAG IDCODE register or the eight-bit ISP register. The device ID assignments are listed in Table 4. The ispJTAG programming is accomplished ...
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Signal Descriptions Signal Name I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK and ...
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I/O Locations: ispGDX160/A 208 272 Signal PQFP BGA Signal PQFP BGA I I/O A32 I I/O A33 I I/O A34 I I/O A35 I I/O ...
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Signal Configuration: ispGDX160/A ispGDX160/A 272-Ball BGA Signal Diagram I/O I/O I I/O I/O I D11 I/O ...
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Pin Configuration: ispGDX160/A ispGDX160/A 208-Pin PQFP (with Heat Spreader) Pinout Diagram Control Data 1 — VCC CLK I I MUXsel1 I MUXsel2 I — GND CLK ...
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Signal Locations: ispGDX120A Signal TOE 150 RESET 156 Y0, Y1, Y2, Y3, 63, 64, 152, 153 BSCAN/ispEN 154 TDI/SDI 69 TCK/SCLK 68 TMS/MODE 67 TDO/SDO 66 GND 8, 17, 27, 37, 50, 65, 77, 91, 101, 110, 120, 129, 144, ...
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Pin Configuration: ispGDX120A ispGDX120A 176-Pin TQFP Pinout Diagram Control Data 1 1 — NC — — VCC 4 CLK I I MUXsel1 I MUXsel2 I ...
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Pin Configuration: ispGDX120A ispGDX120A 160-Pin PQFP Pinout Diagram Control Data — VCC 1 2 CLK I I MUXsel1 I MUXsel2 I — GND 6 CLK 7 I/O A ...
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Signal Locations: ispGDX80A Signal 100-Pin TQFP Y1/TOE RESET 89 BSCAN/ispEN 35 TDI/SDI 39 TCK/SCLK 36 TMS/MODE 86 TDO/SDO 85 GND 6, 18, 29, 45, 56, 68, 79, 95 VCC 12, 37, 62, 88 I/O Locations: ispGDX80A Signal ...
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Pin Configuration: ispGDX80A ispGDX80A 100-Pin TQFP Pinout Diagram Control Data CLK I I MUXsel1 I MUXsel2 I CLK I GND 6 — ...
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Part Number Description ispGDX XXXX Device Family Device Number 160* 160A 120A 80A Speed 5 = 5ns Tpd 7 = 7ns Tpd Ordering Information I/O PINS tpd (ns 160 160A ...