MSM7731-02 OKI [OKI electronic componets], MSM7731-02 Datasheet - Page 27

• Manufacturer Part Number: MSM7731-02
• Description: Dual Echo Canceler & Noise Canceler with Dual Codec for Hands-Free
• Manufacturer: OKI [OKI electronic componets]

(1) CR0 (basic operating mode setting)
Note*5: Initial values are the values set when reset is activated by the PDN/RST pin. (Initial values are
B7
B6
B5
B4
B3
B2
1 Semiconductor
Value (*5)
Initial
CR0
PCMEI/O control
also set in the same manner, except for CR0-B7, when reset by the PDN/RST bit of B7.)
Power-down and Reset
During power-down reset, this device enters the power-down state. At this time all control register bits,
internal variables, and the coefficients for the echo canceler and noise canceler are reset. After power-
down reset is released, this device enters the initial mode. This bit is internally ORed with the inverted
PDN/RST signal. Refer to the section “RELATIONSHIP BETWEEN PINS AND CONTROL
REGISTERS”.
Reset control
At reset, the coefficients for the echo canceler and noise canceler and noise canceler are reset. Control
register contents preserved. While reset is being processed, there is no sound. Use this bit in cases where
the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming
telephone communication. Because data is read by this bit in synchronization with the rising edge of the
SYNC signal, hold the data in the bit for 250 s or longer. This bit is internally ORed with the inverted
RST signal. Refer to the section “RELATIONSHIP BETWEEN PINS AND CONTROL
REGISTERS”.
Line CODEC power-down control
impedance and line CODEC input pin is internally processed as an idle pattern input. This bit is
internally ORed with the LINEEN pin. When the line CODEC is not used, this control results in low
consumption of electrical power. This bit can only be set to “0” or “1” during power-down reset and
initial mode. Refer to the section “RELATIONSHIP BETWEEN PINS AND CONTROL
REGISTERS”.
SYNC, BCLK output control
When OFF, the SYNC and BCLK output pins are in the high impedance state. This control is valid
when the CLKSEL pin is at a logic “0” and has selected the internal clock mode. When the SYNC and
BCLK clocks are not used externally, this control results in low consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial mode.
When OFF, the PCMO output pin is in the high impedance state and the PCMI input pin is internally
processed as an idle pattern input. When the line digital interface is not used, this control results in low
consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial mode.
When OFF, the PCMEO output pin is in the high impedance state and the PCMEI input pin is internally
processed as an idle pattern input. When the line digital interface is not used, this control results in low
consumption of electrical power.
This bit can only be set to "0" or "1" during power-down reset and the initial mode.
During power-down, the line CODEC is in the power-down state, the line CODEC output pin is at high
PCMI/O control
PDN/RST
B7
0
RST
B6
0
LINEEN
B5
0
CLKEN
0: power-on
0: normal operation 1: reset
0: normal operation 1: power-down
0: ON
0:ON
0:ON
B4
0
1: OFF
1: OFF
1: OFF
PCMEN
B3
0
1: power-down reset
PMCEEN
B2
0
MCUSEL
OPE
B1
0
FEDL7731-02-04
MSM7731-02
ECSEL
OPE
B0
0
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