MT90528AG ZARLINK [Zarlink Semiconductor Inc], MT90528AG Datasheet - Page 172

• Manufacturer Part Number: MT90528AG
• Description: 28-Port Primary Rate Circuit Emulation AAL1 SAR
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Table 97 and Table 98 refer to input clock parameters which are displayed in Figure 56 and Figure 57, which follow
the tables.
STiCLK/C4M/C2M Clock Period
STiCLK/C4M/C2M Pulse Width (HIGH / LOW)
Frame Pulse Width
Frame Pulse Setup Time
Frame Pulse Hold Time
Data Setup Time - DSTi/CSTi VALID to STiCLK/C4M/C2M falling
Data Hold Time - STiCLK/C4M/C2M falling to DSTi/CSTi INVALID
Data Setup Time - DSTi/CSTi VALID to STiCLK/C4M/C2M rising
Data Hold Time - STiCLK/C4M/C2M rising to DSTi/CSTi INVALID
1.544 Mbps bus (1.544 MHz clock)
1.544 or 2.048 Mbps bus (2.048 MHz clock)
2.048 Mbps bus (4.096 MHz clock)
1.544 Mbps bus (1.544 MHz clock)
1.544 or 2.048 Mbps bus (2.048 MHz clock)
2.048 Mbps bus (4.096 MHz clock)
1.544 Mbps (Generic)
2.048 Mbps (Generic)
2.048 Mbps (ST-BUS)
STiMF/F0 valid to STiCLK/C4M/C2M rising
STiMF/F0 valid to STiCLK/C4M/C2M falling
STiCLK/C4M/C2M rising to STiMF/F0 invalid
STiCLK/C4M/C2M falling to STiMF/F0 invalid
Sampling on falling edge
Sampling on falling edge
Sampling on rising edge
Sampling on rising edge
Characteristic
Characteristic
Table 97 - TDM Bus Input Clock Parameters
Table 98 - TDM Bus Input Data Parameters
t
STiCKH/L
Zarlink Semiconductor Inc.
t
Sym.
t
STiCK
FPW
t
t
FIS
FIH
MT90528
172
Min.
100
100
100
15
15
10
10
Sym.
t
t
t
t
SIS
SIH
SIS
SIH
Typ.
648
488
244
324
244
122
648
488
244
Min.
15
10
15
10
Typ.
Max.
900
600
300
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
Test Conditions
Test Conditions
Data Sheet