AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet
AM79C850KCW
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AM79C850KCW Summary of contents
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PRELIMINARY Am79C850 SUPERNET 3 DISTINCTIVE CHARACTERISTICS Compliant with the ANSI X3T9.5/ISO 9314 specification — 100 Mbps data rate — Timed token-passing protocol — Ring topology Complete memory management — Supports 256K bytes of local frame buffer memory — Supports buffer ...
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AMD configurations with an external physical layer controller. SUPERNET 3 has a Test Access Port and Boundary Scan Architecture, IEEE1149.1. SUPERNET 3 provides Built-in Self Test (BIST) features for the Address Filter, and PLC-S. All registers are readable and writable ...
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BLOCK DIAGRAM SUPERNET 3 AMD TRST TMS TCK TDO TDI RXAFCU RXAFCL RXAFU[3:0] RXAFL[3:0] XDAMAT XDA_XACT XSAMAT XSA_XACT 3 ...
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AMD Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents (continued) Address Filter Test Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD List of Figures Figure 1. Memory Receive Queue (Modified TAG Mode) Figure 2. Register 3 (MDREG3) Figure 3. Frame Selection Register (FRSELREG) Figure 4. Delay Register (UNLCKDLY) Figure 5. THRU_A Configuration Figure 6. WRAP_A Configuration Figure 7. WRAP_B Configuration ...
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CONNECTION DIAGRAM 208-Pin PQR (Top View SSO 2 NP[15] 3 NP[14] 4 NP[13] NP[12 NP[11] NP[10 CCO 8 NP[9] 9 NP[8] 10 NP[ SSO NP[ NP[5] NP[4] 15 NP[3] ...
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AMD PQFP PIN DESIGNATIONS Listed by Pin Number Pin # Description Pin # 1 VSSO 35 2 NP[15 NP[14 NP[13 NP[12 NP[11 NP[10 VCCO 42 9 NP[9] 43 ...
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PQFP PIN DESIGNATIONS Listed by Pin Number Pin # Description Pin # 137 VCC 155 138 BD[28] 156 139 BD[27] 157 140 BD[26] 158 141 VSS 159 142 BD[25] 160 143 BD[24] 161 144 VSSO 162 145 BD[23] 163 146 ...
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AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C850 K DEVICE NUMBER/DESCRIPTION Am79C850 SUPERNET 3 Valid Combinations AM79C850 KC, KC\W 10 ...
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PIN DESCRIPTION I/O pins can only be high impedance in Test Access Port (TAP) operation. Refer to TAP Testability section. PHY/PMD Interface (46 Pins) RX+, RX- Receive Data (PECL Input) These pins receive differential NRZI data. TX+, TX- Transmit Data ...
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AMD high, the upper nibble of the X-bus is interpreted as a network control character. Otherwise interpreted as a data nibble. XCL Transmit Control Lower (TTL output, high impedance) The XCL output signal is used to flag control ...
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DS Data Strobe/ (TTL input, active low) – Asynchronous when NPMODE = 0 – Synchronous when NPMODE = 1 The DS input (active low) is used in the handshake between the NP and SUPERNET 3 when the SUPERNET 3 acts ...
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AMD change in ring status has occurred. MINTR2 is deacti- vated once either the lower or upper 16 bits of status register 2 (ST2L or ST2U) are read. Once MINTR2 is asserted, all 32 bits of status register 2 must ...
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In transmit mode, when BDTAG = 0, it indicates that the information on the BD bus is data, i.e., end-of-frame not yet reached. CSO Chip-Select Output (TTL output, high ...
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AMD QCTRL2 QCTRL1 QCTRL0 Indicated Status (1) Quiescent. (2) Space remains for more data while loading a transmit queue Unloading transmit frame from Synchro- nous Queue Unloading transmit frame from Asynchro- ...
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RS5–0 Receive Status (TTL output, high impedance) The receive-status (RS4–0) pins indicate the type of frame received, and the condition of the receive state RS5 RS4 RS3 ...
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AMD fashion to the XDAMAT pin. This input is used in conjunction with the XDAMAT pin as follows: Match XDA_XACT and XDAMAT A, C indicators set and frame copied*. XDA_XACT and XDAMAT Invalid combination. Ignored by MAC. XDA_XACT and XDAMAT ...
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TRST Test Reset (asynchronous TTL input, active low) This input is provided for asynchronous initialization of the TAP controller. When a logic 0 is applied, the TAP controller must go to the Test-Logic-Reset state. If for some reason TRST is ...
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AMD RS 5:0 Receive Status pins (outputs) An additional receive status pin has been added to provide more receive information. The encoding of the status pins is fully backward compatible with the RS5 RS4 RS3 ...
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MEIND0 and MEIND1 bits in the mode register 3 (MDREG3). MEIND1 MEIND0 Description 0 0 Default SUPERNET 2 behavior 0 1 Set ONLINE mode. This overrides OSM status indicator setting (i.e., if MDREG1 bits MMODE2=0, MMODE1=1, ...
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AMD MEIND[1:0] OSM EN_XACT ...
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Transmit Queues ASYNC2 Transmit Queue Not Supported The SUPERNET 3 supports SYNCHRONOUS, and two ASYNCHRONOUS priorities. The ASYNC2 queue is no longer supported. This causes the following changes: 1. TPRI2 (16-bit priority register for asynchronous queue longer ...
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AMD Non-Tag Mode of Operation No Longer Supported The SUPERNET 3 only supports the tag mode of operation for transmit and receive. The non-tag mode of operation is no longer supported. All functionality related to the non-tag mode of operation ...
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STATUS WORD 1 FRAME 1 LENGTH FRAME 1 STATUS WORD 2 FRAME 2 LENGTH FRAME 2 STATUS WORD 3 FRAME 3 LENGTH STATUS WORD 4 FRAME ...
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AMD Transmit Command The SUPERNET 3 provides a feature to control transmission of frames from ASYNC1 queue in both TAG and Modified TAG modes. This feature can be enabled by programming the MENTRCMD (bit 14) in mode register 3 (MDREG3). ...
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MSB Figure 2. Register 3 (MDREG3) (NPADDR = 60h) Bit MENRS (bit 0) Enable enhanced Receive status encoding. MENXS (bit 1) Enable enhanced Transmit status encoding. MENXCT (bit 2) Enable EXACT/INEXACT matching. MENAFULL (bit 3) ...
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AMD Address Space The FORMAC Plus uses seven pins (0–6) and the PLC uses five pins (0–4). The new address space uses eight pins (0–7) with the following decoding: Address 7:0 Comment 00–7F MAC addresses 128 addresses can ...
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During the time that the TRANSMIT INHIBIT function is enabled the network timers and state machines operate normally result of the change ...
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AMD MSB Figure 3. Frame Selection Register (FRSELREG) Options for selecting frame types under two receive queues operation is as follows: RECVX3:0 Frame Type 0000 Receive all frames except the frame type selected for other ...
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The two receive queues will have independent receive FIFO’s. There will be two instructions to clear locks on the two receive queues. “Clear Receive Queue Lock” (instruction code 20h) will be for RECV1 and the new instruction” Clear Receive2 Queue ...
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AMD MSB Symbol Control The SUPERNET 3 no longer supports the ability to transmit raw symbols from the Buffer Memory to the PHY. This feature has been removed and the mode bit SYMCTL (bit 5, ...
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RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL SUPERNET 3 MAC Rx Tx X9:0 R9:0 PDTR: Phy Data Transmit and Receive Functions Figure 5. THRU_A Configuration RXAFU 3:0, RXAFL 3:0, RXAFCU, RXAFCL SUPERNET 3 MAC Rx Tx R9:0 X9:0 PDTR: Phy Data ...
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AMD MAC Rx Tx X9:0 PDTR: Phy Data Transmit and Receive Functions MAC Rx Tx X9:0 PDTR: Phy Data Transmit and Receive Functions Changes and Enhancements to PHY Changes from SUPERNET 2 PLC Addition of Scrambler/Descrambler Scrambler/descrambler is implemented. Scrambling/ ...
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Addition of Scrambler/Descrambler Function to Support Copper PMD This is a description of the Stream-Cipher Scrambler and Descrambler as implemented in the physical layer controller block. The Stream-Cipher Scrambler adds the output of a random generator to the data stream. ...
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AMD Instructions Supported This section describes the public and private instruc- tions that are supported in this implementation. The instruction register is a 4-bit register. The least Instruction Description EXTEST External test IDCODE Device identification SAMPLE Sample/preload B.S.R. TRI_ST Force ...
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SHIFT_DR TAP controller state. The BIST result register is 33 bits in length. BYPASS Instruction The BYPASS instruction is used to bypass the SUPER- NET 3 BSR and shorten access times to other devices on a ...
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AMD BSR Cell No. Pin No 100 36 101 37 102 38 103 39 106 40 107 41 108 42 109 43 111 44 112 45 113 46 114 ...
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BSR Cell No. Pin No. 85, 86 142 87, 88 143 89, 90 145 91, 92 146 94 147 95, 96 148 97, 98 150 99, 100 151 101, 102 152 103, 104 153 105 154 106 155 107 N/A ...
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AMD BSR Cell No. Pin No. 151 189 152 190 153 191 154 192 155 194 156 195 157 196 158 197 159 199 160 200 161 201 162 202 163 204 164 205 165 206 166 207 167, 168 ...
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BSR Cell No. Pin No. 207 30 208 32 209 33 210 34 211 35 212 36 213 37 214 38 215 39 216 40 217 41 218 42 219 43 220 44 221 45 222 46 Built-In Self Test ...
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AMD MSB Reserved Bits are Read as Zero Unless Otherwise Stated. Figure 9. Status Register 1 – Upper 16 Bits (ST1U) (NPADDR = 00h) MSB Reserved Bits are Read as ...
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MSB Reserved Bits are Read as Zero Unless Otherwise Stated. Figure 11. Status Register 2 – Upper 16 Bits (ST2U) (NPADDR = 02h) MSB Reserved Bits are Read as Zero ...
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AMD MSB Reserved Bits are Read as Zero Unless Otherwise Stated. Figure 13. Mode Register 1 (MDREG1) (NPADDR = 10h) MSB Reserved Bits are Read as Zero Unless Otherwise Stated. ...
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Status Register 3 (ST3U & ST3L) A 32-bit read only register, designated ST3, and a 32 bit read/write register, designated IMSK3, has been added in SUPERNET 3. This register is dedicated to status handling and interrupt reporting. Any of the ...
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AMD MSB Figure 16. Status Register 3 – Lower 16 Bits (ST3L) (NPADDR = 62h) The following bits are in ST3U (the upper half of ST3). Status Receive Complete (Receive Queue 2) SRCOMP2 (bit 15) ...
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Status Receive Parity Error Queue 2 SRPERRQ2 (bit 3) This bit is set when there is parity error in the data received in queue 2. Status Receive Parity Error Queue 1 SRPERRQ2 (bit 2) This bit is set when there ...
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AMD EACB EARV1 EAS EAA0 EAA1 EARV2 Figure 17. Buffer Memory Queue Organization Parity Generation and Checking The SUPERNET 3 will have the following sequence of parity generation and checking: Transmit Path: The parity, (even or odd) will be checked ...
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In either method, the DS is ignored and should be inactive (HIGH) during all synchronous accesses. The read cycle is initiated by asserting the CSI, NPADDR, NPRW signal which is sampled by the rising edge of the clock. The NPRW ...
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AMD recognizes both source and destination addresses, extending the strip and copy functions of the core FDDI MAC. The content addressable memory (CAM) that contains 32 entries. Each entry consists of a 48-bit comparand, a 48-bit mask ...
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Command Register (AFCMD) The command register is a 16-bit register that may be read and written through the node processor interface. Writing to this register causes the AF to perform the commanded operation. All data necessary for an MSB 15 ...
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AMD INST 2:0 000 Invalidate CAM: This function invalidates all entries in the CAM. The DONE, FULL, FOUND, MULT, ERROR, BISTDONE and EXACT bits in the status register will be cleared when this com- mand is issued. The DONE and ...
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Status Register (AFSTAT) The status register is a 16-bit register that may be read and written through the node processor interface. This MSB Reserved bits are read as zero unless otherwise stated. DONE (bit 15) ...
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AMD MULT (bit 11) Multiple Match This bit reflects the result of a “Find” operation. This bit has meaning only if the FOUND bit is set. If this bit is set, it indicates that more than one entry in the ...
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MSB Figure 20. Node Processor Comparand Register (AFCOMP2) MSB Figure 21. Node Processor Comparand Register (AFCOMP1 ...
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AMD MSB Figure 22. Node Processor Comparand Register (AFCOMP0) Mask Registers (AFMASK2:0) The mask registers are 16-bit registers that may be read and written by the node processor. AFMASK0 corre- sponds to bits 15:0 of ...
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MSB MSB Figure 23. Mask Register (AFMASK2 ...
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AMD MSB Personality Register (AFPERS) The personality register is a 16-bit register that may be read and written by the node processor. This register will be cleared (filled with zeroes reset and will ...
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MSB Reserved Bits are Read as Zero Unless Otherwise Stated. Reserved (bits 15:6) Reserved These bits are reserved for future use. These bits should always be written with zeroes to ensure compatibility with future revisions ...
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AMD Node Processor Register Address Map The registers accessible through the node processor interface are addressed as shown in the table below. Register Mnemonic Address Register Name AFCMD “b0” Address Filter Command Register AFSTAT “b2” Address Filter Status Register AFBIST ...
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Figure 27. AF–MAC Interface Handshake (Internal Signals SUPERNET 3 AMD 19574A-28 61 ...
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AMD ADDRESS FILTER TEST SPECIFICATION Introduction The Address Filter (AF) core requires a special set of test patterns to provide adequate fault coverage. The mask and data bits of the AF are similar to an SRAM cell and must be ...
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BIST Pattern Requirements This section presents the pattern requirements that the BIST implementation should try to meet. The implemen- tation should try to meet as many of the requirements as possible, however, overhead considerations may make this goal unattainable. In ...
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AMD 1. The stuck-at 1 (s@1) condition in the mask bits for a comparator can be checked by first writing all mask bits to 0’s, all data bits to 0’s and the comparand register to all 1’s. If any single ...
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This pattern will take much longer to apply than the minimal set presented in table 2. Destination address exact/inexact logic: Since the destination address matching logic is identical to the source ...
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AMD PDX FUNCTIONAL DISCRIPTION Introduction The PDX is a digital CMOS core that is used in SUPERNET 3. It employs new circuit techniques to achieve clock and data recovery. Traditionally, Phase-Locked-Loops (PLL) are used for the purpose of clock recovery ...
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Default Timer and Register Values The following are the default timer/register values on power-up reset. Timer/Register MIR (1–0) register TMAX register TVX register and timer TRT timer (bit 20–5) THT timer TNEG register (bit 20–5) TMRS register TREQ0 register TREQ1 ...
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AMD Timer/Register MDREG1 MDREG2 MDREG3 STMCHN FCNTR LCNTR ECNTR FSCNTR EACB, EARV1, EAS, EAA0, EAA1, EARV2 SACL, SABC RPR1, WPR1, SWPR1 RPR2, WPR2, SWPR2 WPXS, WPXA0, WPXA1 SWPXS, SWPXA0, SWPXA1 RPXS, RPXA0, RPXA1 MARR, MARW WPXSF, RPXSF FRMTHR Notes: *1 ...
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SUPERNET 3 REGISTERS SUPERNET 3 Programmable Registers Register Mnemonic NPADDR7–0 “cmdreg1” “00” “cmdreg2” “01” “st1u” “00” “st1l” “01” “st2u” “02” “st2l” “03” “imsk1u” “04” “imsk1l” “05” “imsk2u” “06” “imsk2l” “07” “said” “08” “laim” “09” “laic” “0a” “lail” “0b” “sagp” “0c” ...
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AMD SUPERNET 3 Programmable Registers (continued) Register Mnemonic NPADDR7–0 “pri1” “1d” “pri2” “1e” “tsync” “1f” “mod2” “20” “frmthr” “21” “eacb” “22” “earv1” “23” “eas” “24” “eaa0” “25” “eaa1” “26” “eaa2” “27” “sacl” “28” “sabc” “29” “wpxsf” “2a” “rpxsf” “2b” “rpr1” ...
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SUPERNET 3 Programmable Registers (continued) Register Mnemonic NPADDR7–0 “fcntr” “41” “lcntr” “42” “ecntr” “43” “fscntr” “44” “frselreg” “45” “46” “46” “47” “47” “48” “48” “49” “49” “4a” “4a” “4b” “4b” “4c” “4c” “4d” “4d” “4e” “4e” “4f” “4f” “50l” “50” ...
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AMD SUPERNET 3 Programmable Registers (continued) Register Mnemonic NPADDR7–0 “imsk3l” “64” “ivr” “65” “imr” “66” “ilr” “67” “rpr2” “68” “wpr2” “69” “swpr2” “6a” “earv2” “6b” “unlckdly” “6c” “6d” “6d” “6e” “6e” “lwpr1” “6f” “lrwd1” “70” “lwpr2” “71” “lrwd2” “72” “fifoflag” ...
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SUPERNET 3 Programmable Registers (continued) Register Mnemonic NPADDR7–0 “c_min” “86” “tl_min” “87” “tb_min” “88” “t_out” “89” “plc_cntrl_c” “8a” “lc_length” “8b” “t_scrub” “8c” “ns_max” “8d” “tpc_load_value” “8e” “tne_load_value” “8f” “plc_status_a” “90” “plc_status_b” “91” “tpc” “92” “tne” “93” “clk_div” “94” “bist_signature” “95” ...
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AMD SUPERNET 3 Programmable Registers (continued) Register Mnemonic NPADDR7–0 “orstat” “d2” “d3–df” Description PDX Status Register Reserved for future use SUPERNET 3 ...
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SUPERNET 3 COMMAND REGISTERS SUPERNET 3 Command Registers 1 Instruction Name Software Reset Load MDR from buffer memory with MARR increment Load MDR from buffer memory without MARR increment Idle/Listen Claim/Listen Beacon/Listen Load TVX timer from TVX register Nonrestricted Token ...
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AMD Revision I.D. The bits 13, 14 the State Machine Register provides a three-bit binary value that indicates the revision number of the SUPERNET 3. The revision I.D. shall be ‘111’ for the first revision. The PLC_STATUS_A register, ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature . . . . . . . . . . . . . . Supply Voltage Referenced ...
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AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Must be Steady May Change from May Change from Don’t Care, Any Change Permitted Does ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Clocks Parameter No. Symbol Parameter Description 1 t LSCLK Period PER 2 t LSCLK High Pulse Width PWH 3 t LSCLK Low Pulse Width PWL 4 t BCLK Period PER 5 t BCLK High ...
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AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges NP Parameter No. Symbol Parameter Description R/W and NPADDR[7:0] Setup Time to DS (CSI) Low DS(CSI) Low to NPDATA[15:0] Enabled (Asynchronous Read DS(CSI) Low to NPDATA[15:0] Valid ...
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SWITCHING WAVEFORMS CSI DS 26 R/W NPADDR 28 NPDATA 27 READY Note 1 Notes: 1. 26, 27, 28, and 30 are measured from CSI or DS whichever goes LOW last. 2. 31, 33, 34, and 32 are measured from CSI ...
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AMD SWITCHING WAVEFORMS CSI DS 26 R/W NPADDR 36 NPDATA READY Note 1 Notes: 1. 26, 36, and 30 are measured from CSI or DS whichever goes LOW last. 2. 31, 32, and 37 are measured from CSI or DS ...
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SWITCHING WAVEFORMS 4 BCLK 38 CSI 39 R/W 41 NPADDR 40 NPDATA 42 READY Note ignored in Synchronous mode and should be inactive (High) during all Synchronous accesses. Figure 31. NP Synchronous Read and Write Except MDR ...
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AMD 4 BCLK 38 CSI 39 R/W 41 NPADDR 40 NPDATA 42 READY Notes ignored in Synchronous mode and should be inactive (High) during all Synchronous accesses. 2. Read and Write Cycles could extend beyond two clock ...
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SWITCHING WAVEFORMS 4 BMCLK 53 NPMEMREQ NPMEMACK CSO RD WR ADDR Figure 33. NP DMA Signals SUPERNET 3 AMD 54 56 19574A-34 ...
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AMD SWITCHING WAVEFORMS 4 BMCLK MINTR[4:1] 50 RST Figure 34. NP Miscellaneous Signals SUPERNET 3 Open Drain 51 19574A-35 ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Host Interface & Buffer Memory Parameter No. Symbol Parameter Description 76 t HSREQ2–0 Setup Time to BMCLK High HSREQ2–0 Hold Time to BMCLK High BMCLK High to HSACK ...
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AMD SWITCHING WAVEFORMS BMCLK 76 HSREQ HSACK ADDR15–0 CSO RDATA QCTRL2– 123 87 122 93 121 80 82 Figure 35. ...
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SWITCHING WAVEFORMS BMCLK ADDR15-0 CSO RD BD31-0, BDP3-0, BDTAG Figure 36. Buffer Memory Read Cycle Timings BMCLK ADDR15-0 CSO WR BD31-0, BDP3-0, BDTAG Figure 37. Buffer Memory Write Cycle Timings ...
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AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges External PHY Interface Timing Parameter No. Symbol Parameter Description 126 t BCLK High to X–Bus (X0–7, XCU, XCL) Valid PD 127 t X–Bus (X0–7, XCU, XCL) Invalid from BCLK High PD 130 t ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges MAC Miscellaneous Signal Timing Parameter No. Symbol Parameter Description 140 t FLXI/XMTINH Setup Time to BCLK High S 141 t FLXI/XMTINH Hold Time from BCLK High H 142 t BCLK High to RS5–0, XS3–0 ...
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AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges External CAM Interface Timing Parameter No. Symbol Parameter Description 156 t BCLK High to RXAFU3–0, RXAFL3–0, RXAFCU, RXAFCL Valid PD 157 t RXAFU3–0, RXAFL3–0, RXAFCU, RXAFCL Invalid from PD BCLK High SWITCHING WAVEFORMS ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PHY Miscellaneous Signal Timing Parameter No. Symbol Parameter Description FOTOFF, LSR 2–0, ULSB, EBFERR Valid from BCLK High 200 t PD FOTOFF, LSR 2–0, ULSB, EBFERR Invalid from BCLK High 201 t PD 210 ...
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AMD SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Test Interface Signal Timing Parameter No. Symbol Parameter Description 226 t TCLK Period PER 227 t TCLK Pulse Width High PWH 228 t TCLK Pulse Width Low PWL TDI, TMS, TRST Setup Time ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PMD Interface Signal Timing Parameter No. Symbol Parameter Description 250 t TX+, TX– Rise Time R 251 t TX+, TX– Fall Time F 252 t TX+ to TX– Skew SK 253 t SDI Setup ...
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AMD REFERENCES PHY Device 1] AMD Am79C864A in The SUPERNET 2 Family for FDDI , Publication no. 15502, Rev. C, Physical Layer Controller with Scrambler/ Descrambler (PLC-S). 2] ANSI X3.148-1988, FDDI Physical Layer Specification. 3] ANSI X3T9 SMT Ver. 7.2, ...
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PHYSICAL DIMENSIONS* PQR208, Trimmed and Formed 208-Pin Plastic Quad Flat Pack (measured in millimeters) Pin 208 25.50 REF Pin 1 I.D. Pin 52 3.20 3.60 0.25 Min *For reference only. BSC is an ANSI standard for Basic Space Centering. Trademarks ...