AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 46

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

The following bits are in ST3U (the upper half of ST3).
Status Receive Complete (Receive Queue 2)
SRCOMP2 (bit 15)
This bit is set at the completion of a frame reception
following the writing of the frame status and length.
Receive frames that are aborted set this bit, but flushed
frames do not. This is valid in tag and modified
tag mode.
Status Receive Buffer Empty (Receive Queue 2)
SRBMT2 (bit 14)
This bit is set when the receive buffer is empty (i.e.
RPR2 = WPR2 after an increment of RPR), and is reset
when frames are in the receive buffer. This bit is not
auto-cleared when read. An interrupt is generated due
to setting of this bit when read from the receive queue is
attempted while the receive buffer is empty.
Status Receive Abort (Receive Queue 2)
SRABT2 (bit 13)
The SRABT2 bit is set when the frame being received is
aborted. Frames that normally would be flushed but are
aborted due to threshold criterion in tag mode would set
this bit.
46
MSB
15
AMD
14
13
Figure 16. Status Register 3 – Lower 16 Bits (ST3L) (NPADDR = 62h)
12
11
10
9
P R E L I M I N A R Y
8
SUPERNET 3
7
6
Status Receive Buffer Full (Receive Queue 2)
SRBFL2 (bit 12)
This bit is set when the receive buffer is full (RPR2 =
WPR2 after an increment of WPR2). The buffer-mem-
ory receive queue is then locked for further input.
SRBFL2 can be cleared using the clear receive queue
lock (20h) or clear all queue locks (3fh) commands, or by
using the auto-unlock feature.
Status Receive FIFO Overflow (Receive Queue 2 )
SRCVOVR2 (bit 11)
This bit when set, indicates that the SUPERNET 3
receive 2 FIFO has overflowed and receive data has
been lost. This condition may occur during the receive
buffer full state. SUPERNET 3 will not set the frame-
status C indicator (frame copied) on repeated frames
when this bit is set.
Reserved (bit 10–bit 4)
These bits are reserved for future use. Some of these
reserved bits may read zero or one and the user should
ignore these bits. The corresponding mask register bits
should be programmed to mask out the interrupts from
these bits.
5
4
3
2
1
0
LSB
AF_BIST_DONE
PLC_BIT_DONE
SICAMDAXACT
SICAMSAXACT
SICAMDAMAT
SICAMSAMAT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
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