AM79C864AKCW AMD [Advanced Micro Devices], AM79C864AKCW Datasheet
AM79C864AKCW
Related parts for AM79C864AKCW
AM79C864AKCW Summary of contents
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PRELIMINARY Am79C864A Physical Layer Controller With Scrambler (PLC-S) DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 Implements ANSI standard Stream Cipher Scrambling/Descrambling Hardware Physical Connection Management (PCM) support Performs Physical Connection insertion and removal On-chip Link ...
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AMD PLC-S chip during Link Confidence Test and after the link has been formed, to detect a noisy link. The PLC-S contains a Line State Machine for detecting received line states and a Data Stream Generator for transmitting the various ...
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PLC-S CORE BLOCK DIAGRAM Receive EB Data Local Input Lbmux Framer IRDAT 5 Misc Status and Control NP PCM 16 NPADDR Error Counters 5 and Timers Control Signals NP Interface ITDAT 5 Transmit Data Test Data Output Mux P R ...
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AMD DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION PLC-S BLOCK DIAGRAM PLC-S CORE BLOCK DIAGRAM TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TABLE OF CONTENTS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD CONNECTION DIAGRAM 120-Pin PQR (Top View INT 2 3 NPADDR4 4 NPADDR3 5 NPADDR2 6 NPADDR1 NPADDR0 TDAT0 10 11 TDAT1 12 TDAT2 13 TDAT3 TDAT4 ...
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PQFP PIN DESIGNATIONS Listed by Pin Number Pin Number Pin Name Pin Number 1 VSS 31 INT NPADDR4 33 NPADDR3 34 4 NPADDR2 35 5 NPADDR1 36 6 VDD 7 37 VSS NPADDR0 39 ...
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AMD LOGIC SYMBOL BCLK NPCLK RSCLK LSCLK RDAT 4–0 TX 9–0 TXPAR CS NPRW NPADDR 4–0 RST SDO TEST 2–0 RRSCLK SCRM ENCOFF VDD VSS 3-10 The SUPERNET 2 Family for FDDI 1994 Data Book ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C864A DEVICE NUMBER/DESCRIPTION Am79C864A Physical Layer Controller With Scrambler (PLC-S) Valid Combinations AM79C864A KC, ...
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AMD PIN DESCRIPTION Clock Signals BCLK Byte Clock (Input) BCLK is a 12.5 MHz clock used by the PLC-S to clock most internal operations, clock RX 9–0 to the MAC device and, along with LSCLK, latch TX 9–0 ...
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NP 15–0 Node Processor Data Bus (Input/Output, Three State) The NP 15–0 bus is a sixteen bit bi-directional, three- state data bus used to exchange data between the PLC-S and the Node Processor. NPRW Node Processor Read/Write (Input) The NPRW ...
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AMD RRSCLK Reserved (Input) This pin should be connected to VSS. Control and Status Signals EBFERR Elasticity Buffer Error (Output, Active High) EBFERR indicates when an overflow or underflow con- dition occurs in the Elasticity Buffer. ENCOFF Encoder Off (Input, ...
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FUNCTIONAL DESCRIPTION Node Processor Interface (NPI) The Node Processor Interface serves as the interface between an external Node Processor and the PLC-S. The interface is a general purpose synchronous interface. The Node Processor Interface is controlled by the NPCLK. In ...
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AMD NPRW = NPRW = NPRW = 1 Read1 Drive NP Read2 Read4 Read5 Figure 1. Node Processor Interface State Machine 3-16 The ...
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Registers The PLC-S contains twenty-six 16 bit registers ad- dressed from (hex). These registers are listed in Table 1. Table 1. PLC-S Registers Address (hex) Name 00 PLC_CNTRL_A 01 PLC_CNTRL_B 02 INTR_MASK 03 XMIT_VECTOR 04 VECTOR_LENGTH 05 ...
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AMD Addr (Hex) NOISE TNE-16 TPC-16 REQ TIMER BIT BIT SCRUB Bit Name Definition 15 Reserved 14 NOISE_TIMER The NOISE_TIMER bit allows the noise timing function of the PCM to be used when ...
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Bit Name Definition The setting of this bit will cause the assertion of the FOTOFF output pin of the PLC-S. 06 FOT_OFF Read PLC_CNTRL_C register description for behavior of this signal when scrambling/ descrambling is enabled. 05 EB_LOC_LOOP When EB_LOC_LOOP ...
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AMD PLC-S Control Register B (PLC_CNTRL_B) PLC_CNTRL_B has address 01 (hex readable and writeable. All bits of this register are cleared with the as- sertion of RST. PLC_CNTRL_B contains signals and re- quests to direct the process of ...
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Bit Name Definition 07 CLASS_S When CLASS_S is set, signifying that the PHY is a single attach station, the station will not be bypassed before the PCM gets to the ACTIVE state. Note that this bit has effect when the ...
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AMD Bit Name Definition 01–00 PCM_CNTRL PCM_CNTRL controls the PCM state machine. When set to a value other than zero, it will cause the PCM to immediately make a transition to the BREAK, TRACE or OFF state. The transition to ...
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PLC-S Control Register C (PLC_CNTRL_C) PLC_CNTRL_C has address OA (hex readable and writeable. Bits 1 through 15 are cleared with the as- sertion of RST. Bit 0 (CIPHER_ENABLE) assumes the same value as SCRM after RST is asserted. ...
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AMD PLC-S Status Register A (PLC_STATUS_A) PLC_STATUS_A has address 10 (hex read-only used to report status information to the Node Proc- essor about the Line State Machine (LSM). Addr (Hex) 10 REVISION_ID ...
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PLC-S Status Register B (PLC_STATUS_B) PLC_STATUS_B has address 11 (hex read-only. It contains signals and status from the Repeat Filter and Physical Connection Management state machine (PCM). Addr (Hex PCI PCI PCI 11 STATE STATE STATE ...
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AMD Bit Name Definition 06 PCM_SIGNALING PCM_SIGNALING is a flag from the PCM indicating that the XMIT_VECTOR register has been written. The XMIT_VECTOR and VECTOR_LENGTH registers cannot be written when this flag is set. 05 LSF The Line State Flag ...
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The value in the TNE Clock Divider is contained in bits 9 and 8 of the CLK_DIV at address 14 (hex). The TNE Timer is used to time the length of (potential) noise events while the PCM is in the ...
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AMD for the short LCT. For medium LCT, it has a recom- mended value of 500 ms (A0A2 hex in 2’s complement). Scrub Time Register (T_SCRUB) The Scrub Time (T_SCRUB) register has address 0C (hex). It has a recommended value ...
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INTR_EVENT register is set whenever the counter increments or whenever the counter overflows (reaches 256), depending on the VSYM_CTR_INTRS bit in the PLC_CNTRL_A register. When the counter overflows it wraps to zero and contin- ues to count. The Violation Symbol ...
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AMD Link Error Event Threshold Register (LE_THRESHOLD) The Link Error Event Threshold register has address 05 (hex readable and writeable and is cleared on the assertion of RST. Bits 7 through 0 of this register contain a value ...
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Addr (Hex MINI VSYM 17 LSDO ERR CTR CTR CTR Bit Name Definition 15 NP_ERR An event indicating that the Node Processor has requested a read or write to an invalid register. This ...
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AMD Interrupt Mask Register (INTR_MASK) The Interrupt Mask Register (INTR_MASK) has ad- dress 02 (hex readable and writeable. It allows the disabling of interrupts caused by specific events. The INTR_MASK contains a bit that corresponds to each bit ...
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Line State Machine (LSM) In the FDDI network, a special group of symbols called Line State Symbols (Q – Quiet, H – Halt, I – Idle) are transmitted to establish the physical connection be- tween neighboring stations. These Line State ...
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AMD The FDDI SMT ANSI Standard defines the following types of physical attachment: A. Dual ring PHY entity connected to Primary Ring In, Secondary Ring Out B. Dual ring PHY entity connected to Secondary Ring In, Primary Ring Out M. ...
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The Physical Connection Insertion (PCI) State Machine works in conjunction with the PCM State Machine. It controls ring scrubbing and the insertion and removal of a station on the ring. PCM Operation The PLC-S implements the PCM state machine as ...
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AMD connection is acceptable and flags the next bit. On re- ceipt of the corresponding bit from the neighbor, the node processor decides the length of the Link Confi- dence Test and communicates it through the next two bits. On ...
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State Description The PCM enters the OFF state whenever the RST pin is asserted or whenever the PC0(OFF) PCM_CNTRL field of the PLC_CNTRL_B register is set to 11 (PC_Stop). The PCM stays in this state until PC_Start is issued or ...
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AMD continue for T_SCRUB length of time and then enter the REMOVED state. PCI Operation for Class S Type Station For a Class S type station, the PCI Operation is same as above with one exception. Normally, for a Non-Class ...
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Reset Inserted PCI3 Notes: 1. Class = S or PCM_MAINT 2. Not (SC_ JOIN and not START_SCRUBBING) 3. SET_SC_ JOIN 4. TPC > T_SCRUB and (SC_JOIN and not START_SCRUBBING) 5. SET_SC_ JOIN 6. Not SET_SC_JOIN and START_SCRUBBING 7. TPC > ...
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AMD Table 15. 4B/5B Decoding of Data Symbol Encoded Input ...
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FCC. The peaks in the radiated signal can be reduced signifi- cantly by scrambling the transmitted signal. Scramblers add the output of a random generator ...
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AMD Using the Stream Cipher Scrambler The system has access to the scrambler and descrambler through a pin and a register. Pin 41 (SCRM) and bit 0 (CIPHER_ENABLE) PLC_CNTRL_C enable the scrambler. SCRM and Table 18. Stream Cipher Enable SCRM ...
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Idle symbols appears before the ending delimiter, then it changes the previous symbol pair to Idles. After passing through Re- peat Filters in other stations, the fragment will eventually be completely converted ...
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AMD register, the PCI is in the INSERT_SCRUB or REMOVE_SCRUB state, the output of the Scrub MUX is Idle symbols. Otherwise transmit data from the BYPASS_MUX is placed on the Receive Data Output Latch. This MUX is used when the ...
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Signature Generator. The test data are input to the transmit data path via the Re- mote Loopback MUX. The test data are fed back to the Signature Generator before the transmit data path ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature . . . . . . . . . . . . . . . Supply Voltage Referenced ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol Parameter Description 1 BCLK Period 2 BCLK Pulse Width Low 3 BCLK Pulse Width High 4 NPCLK Period 5 NPCLK Pulse Width Low 6 NPCLK Pulse Width High 7 LSCLK Period 8 ...
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AMD KEY TO SWITCHING WAVEFORMS SWITCHING WAVEFORMS NPCLK BCLK 13 LSCLK RSCLK 3-48 The SUPERNET 2 Family for FDDI 1994 Data Book WAVEFORM INPUTS OUTPUTS Must be Will be ...
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SWITCHING WAVEFORMS BCLK LPBCK FOTOFF, SCANO LSR, ULSB, EBFERR 34 SDO TEST2-0 ENCOFF PLC-S Misc Signals Timing Diagram Am79C864A AMD 2 ...
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AMD SWITCHING WAVEFORMS 4 NPCLK NPRW 17 16 NPADDR NP INT RST 3-50 The SUPERNET 2 Family for FDDI 1994 Data Book ...
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SWITCHING WAVEFORMS 10 RSCLK 30 RDAT BCLK RX RXPAR 7 LSCLK 28 TX TXPAR 36 TDAT PLC-S Data ...
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AMD SWITCHING TEST CIRCUIT From Output Under Test Note for all bidirectional or output pins. L 3-52 The SUPERNET 2 Family for FDDI 1994 Data Book ...
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SWITCHING TEST WAVEFORMS 3.0 V 1.5 V 0.0 V 1.5 V Enabled Input Bus In High- Impedance State Input Bus Valid Input Waveform Test Points Output Bus In High- ...