AM79C864AKCW AMD [Advanced Micro Devices], AM79C864AKCW Datasheet - Page 15

• Manufacturer Part Number: AM79C864AKCW
• Description: Physical Layer Controller With Scrambler (PLC-S)
• Manufacturer: AMD [Advanced Micro Devices]

Registers
The PLC-S contains twenty-six 16 bit registers ad-
dressed from 00 to 1A (hex). These registers are listed
in Table 1.
Notes:
1. Writable only when the PCM_SIGNALING bit in the
2. Writable only when the PCM is in the MAINT state.
3. Writable only when the PCM is in the MAINT state and
4. Register cleared on read.
Address
(hex)
PLC_STATUS_B register is not set.
the NOISE_TIMER bit in the PLC_CONTROL_A
register is not set.
18
0C
0D
00
01
02
03
04
05
06
07
08
09
0A
0B
0E
0F
10
11
12
13
14
15
16
17
19
1A
Name
PLC_CNTRL_A
PLC_CNTRL_B
INTR_MASK
XMIT_VECTOR
VECTOR_LENGTH
LE_THRESHOLD
C_MIN
TL_MIN
TB_MIN
T_OUT
PLC_CNTRL_C
LC_LENGTH
T_SCRUB
NS_MAX
TPC_LOAD_VALUE
TNE_LOAD_VALUE
PLC_STATUS_A
PLC_STATUS_B
TPC
TNE
CLK_DIV
BIST_SIGNATURE
RCV_VECTOR
INTR_EVENT
VIOL_SYM_CTR
MIN_IDLE_CTR
LINK_ERR_CTR
Table 1. PLC-S Registers
Type
read/write
read/write
read/write
read/write (Note 1)
read/write (Note 1)
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
write only (Note 2)
write only (Note 3)
read only
read only
read only
read only
read only
read only
read only
read only (Note 4)
read only (Note 4)
read only (Note 4)
read only (Note 4)
P R E L I M I N A R Y
Am79C864A
PLC-S Control and Status Registers
The control and status information for the PLC-S is con-
tained in four registers.
PLC-S Control Register A (PLC_CNTRL_A)
PLC_CNTRL_A has address 00 (hex). It is readable and
writable. All bits of this register are cleared with the as-
sertion of RST. PLC_CNTRL_A is used for the following
functions:
Note that several bits of this register can only be written
if the PCM is in the OFF or MAINT state. If this register is
written when the PCM is in any other state these bits will
remain unchanged.
The PLC_CNTRL_A register bit assignments are listed
in Table 2.
Timer configuration
Counter interrupt frequency
PLC-S data path configuration
Execution of PLC-S Built In Self Test
Specification of PCM MAINT state options
AMD
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