ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet
ZL50052GAC
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ZL50052GAC Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs ZL50052GAC • Constant 2-frame throughput delay for frame integrity • ...
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Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard • Memory Built-In-Self-Test (BIST), controlled via microprocessor register • 1.8 V core supply voltage • 3.3 V I/O supply voltage • tolerant inputs, outputs and I/Os Applications ...
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Device Overview The ZL50052 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports operate at 32.768 Mbps. The ZL50052 contains two data memory blocks (Backplane and Local) to provide the following switching path ...
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Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Control Register (CR ...
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Figure 1 - ZL50052 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Local and Backplane Output Enable Control Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pinout Diagram: (as viewed through top of package) A1 corner identified by metallized marking, mold indent, ink dot, or right-angled corner BSTo1 BSTo2 BSTo5 BSTo0 C IC_GND BSTo7 IC_ OPEN D IC_GND BSTo6 IC_ ...
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Pin Description ZL50052 Package Pin Name Coordinates (196 ball PBGA) Device Timing C8i P10 FP8i M10 C8o N10 FP8o N11 C16o M9 ZL50052 Description Master Clock (5 V Tolerant Schmitt-Triggered Input) This pin accepts an 8.192 MHz clock. The internal ...
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Pin Description (continued) ZL50052 Package Pin Name Coordinates (196 ball PBGA) FP16o P12 Backplane and Local Inputs BSTi0-7 G1, H1, H2, H3, J1, J2, K1, J3 LSTi0-7 K14, J13, J14, K13, M14, J12, L14, M13 Backplane and Local Outputs and ...
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Pin Description (continued) ZL50052 Package Pin Name Coordinates (196 ball PBGA) LORS H13 LSTo0-7 B13, B14, D14, C14, D12, E14, D13, E13 Microprocessor Port Signals A0 - A14 B1, B4, B5, D5, A3, A4, C6, B6, A5, A6, C7, B7, ...
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Pin Description (continued) ZL50052 Package Pin Name Coordinates (196 ball PBGA) RESET C9 JTAG Control Signals TCK B11 TMS A11 TDi B10 TDo A12 TRST A14 Power and Ground Pins V D6, D7, D8, DD_IO D10, E4, E11, F4, F11, ...
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Pin Description (continued) ZL50052 Package Pin Name Coordinates (196 ball PBGA) V (GND) D4, D11, E5, SS E10, F6, F7, F8, F9, G6, G7, G8, G9, H6, H7, H8, H9, J6, J7, J8, J9, K5, K10, L4, L11, P1, P13, ...
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In this system, the Backplane and Local input streams are combined, and the Backplane and Local output streams are combined, so that the switch appears input stream by 16 output stream switch. This gives the maximum 8,192 ...
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Blocking Bi-directional Configuration The ZL50052 can be configured as a blocking bi-directional switch application requirement. For example, it can be configured bi-directional blocking switch, as shown in Figure ...
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Local-to-Backplane Path The device can provide data switching between the Local input port and the Backplane output port. The Backplane Connection Memory determines the switching configurations. 2.1.4 Backplane-to-Backplane Path The device can provide data switching between the Backplane input ...
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For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated otherwise. In addition, the ...
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GCI-Bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits ...
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When SMPL_MODE = LOW (input bit fractional delay mode) , bits LID[4:0] and BID[4:0] in the LIDR0 - 7 and BIDR0 - 7 registers respectively define the input bit fractional delay of the corresponding Local and Backplane stream. The total ...
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SMPL_MODE = LOW FP8i C8i BSTi/LSTi0-7 1 BID[4:0]/LID[4:0] = 00000 B Bit delay = 0 bit (Default) BSTi/LSTi0-7 BID[4:0]/LID[4:0] = 00011 B Bit Delay = 3/4 bit SMPL_MODE = HIGH FP8i C8i BSTi/LSTi0-7 1 BID[4:0]/LID[4:0] = 00000 B 3/4 sampling ...
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FP8o System Clock 131.072 MHz BSTo/LSTo0-7 Bit 1 Bit Advancement = 0 (Default) BSTo/LSTo0-7 Bit 1 Bit Advancement = -1 BSTo/LSTo0-7 Bit Advancement = -2 Bit 1 Ch511 BSTo/LSTo0-7 Bit 1 Bit Advancement = -3 Figure 10 - Local and ...
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RESET ODE (input pin) (input pin Table 1 - Local and Backplane Output Enable Control Priority (continued) 5.0 Data Delay Through the Switching Paths Serial data which goes into the device is ...
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Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay time between the input channel being written and the output channel being read exceeds 2 frames. Frame Frame N Serial ...
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Initialization Upon power-up, the device should be initialized by applying the following sequence: 1 Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller. 2 Set ODE pin to LOW. This sets the LSTo0-7 outputs to ...
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Connection Memory The device includes two connection memories, the Local Connection Memory and the Backplane Connection Memory. 8.1 Local Connection Memory The Local Connection Memory (LCM 16-bit wide memory with 4,096 memory locations to support the Local ...
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Memory Block Programming Procedure • Set the MBP bit in the Control Register from LOW to HIGH. • Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits, LBPD[2:0], of the ...
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Test Access Port (TAP) The Test Access Port (TAP) consists of four input pins and one output pin described as follows: • Test Clock Input (TCK) TCK provides the clock for the TAP Controller and is independent of any ...
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The Device Identification Register The JTAG device ID for the ZL50052 is 0C38414B Version, Bits <31:28>: 0000 Part No., Bits <27:12>: 1100 0011 1000 0100 Manufacturer ID, Bits <11:1>: 0001 0100 101 Header, Bit <0> (LSB): 1 10.3 Boundary ...
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Local Data Memory Bit Definition The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input streams and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the ...
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Bit Name 15 LSRC Local Source Control Bit When LOW, the source is from the Backplane input port (Backplane Data Memory). When HIGH, the source is from the Local input port (Local Data Memory). Ignored when LMM is set HIGH. ...
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Bit Name 13 BE Backplane Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the BORS pin. When HIGH, the channel is active. 12:9 BSAB[3:0] ...
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Detailed Register Descriptions This section describes the registers that are used in the device. 13.1 Control Register (CR) Address 0000 . H The Control Register defines which memory accessed. It initiates the memory block programming mode ...
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Reset Bit Name Value 4 MBP 0 Memory Block Programming When LOW, the memory block programming mode is disabled. When HIGH, the connection memory block programming mode is ready to program the Local Connection Memory (LCM) and the Backplane Connection ...
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ZL50052 (a) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL) = ...
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Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (f) Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i ...
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Block Programming Register (BPR) Address 0001 . H The Block Programming Register stores the bit patterns to be loaded into the connection memories when the Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the ...
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Local Input Bit Delay Registers (LIDR0 to LIDR7) Addresses 0023 to 002A . H H There are 8 Local Input Delay Registers (LIDR0 to LIDR7). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling ...
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LIDn LID4 LID3 LID2 LID1 ...
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Backplane Input Bit Delay Registers (BIDR0 to BIDR7) Addresses 0063 to 006A H H There are 8 Backplane Input Delay Registers (BIDR0 to BIDR7). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point ...
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Table 16 illustrates the bit delay and sampling point selection. BIDn BID4 BID3 BID2 ...
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Local Output Advancement Registers (LOAR0 to LOAR7) Addresses 0083 to 008A . Local Output Advancement Registers (LOAR0 to LOAR7) allow users to program the output advancement for output data streams LSTo0 to LSTo7. The possible adjustment ...
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Backplane Output Advancement Registers (BOAR0 - BOAR7) Addresses 00A3 to 00AA Backplane Output Advancement Registers (BOAR0 to BOAR7) allow users to program the output advancement for output data streams BSTo0 to BSTo7. The possible adjustment is ...
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Memory BIST Register Address 014D . H The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to start MBIST: the first with only bit 12 (LV_TM) set HIGH (i.e. 1000h); the second ...
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Reset Bit Name Value 2 BISTSCL 0 Local Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. 1 BISTCCL 0 Local Connection Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion ...
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DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Core Supply Voltage 2 I/O Supply Voltage 3 PLL Supply Voltage 4 Input Voltage (non-5 V tolerant inputs) 5 Input Voltage (5 V tolerant inputs) 6 Continuous Current at digital outputs ...
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DC Electrical Parameters Characteristics 1a Supply Current I 1b Supply Current Supply Current U 1d Supply Current T 2 Input High Voltage S 3 Input Low Voltage 4 Input Leakage (input pins) Input Leakage (bi-directional pins) Weak ...
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AC Electrical Characteristics AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low Input and Output Clock Timing Characteristic 1 FP8i, Input Frame Pulse Width 2 Input ...
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Input and Output Clock Timing (continued) Characteristic 17 FP16o Frame Pulse Width 18 FP16o Output Delay (from frame pulse edge to output frame boundary) 19 FP16o Output Delay (from output frame boundary to frame pulse edge) 20 C16o Clock Period ...
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FP8i (244 ns) t IFPS244 FP8i (122 ns) t ICL C8i CK_int * FP8o (244 ns) t FPFBF8_244 FP8o (122 ns) t OCL8 C8o FP16o (122 ns) FP16o (61 ns) t FPFB16_61 t t OCL16 OCH16 C16o Note *: CK_int ...
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FP8i (244 ns) FP8i (122 ns) t ICL C8i CK_int * FP8o (244 ns) FP8o (122 ns) t OCL8 C8o FP16o (122 ns) FP16o (61 ns) t FPFB16_61 t t OCH16 OCL16 C16o Note *: CK_int is the internal clock ...
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Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point 2 Local/Backplane Serial Input Set-up Time 3 Local/Backplane Serial Input Hold Time 4 Output Frame Boundary Offset 5 Local/Backplane Serial Output Delay FP8i C8i CK_int * L/BSTi0-7 2 ...
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FP8i C8i CK_int * L/BSTi0 32.768 Mbps FP8o C8o CK_int * L/BSTo0-7 Bit5 Bit6 32.768 Mbps Ch511 Ch511 Note *: CK_int is the internal clock signal of 131.072 MHz. Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32 ...
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Local and Backplane Output High-Impedance Timing Characteristic 1 STo delay - Active to High-Z - High-Z to Active 2 Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Note 1: High Impedance is measured ...
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Input Clock Jitter Tolerance Jitter Frequency 1 1 kHz 2 10 kHz 3 50 kHz 4 66 kHz 5 83 kHz 6 95 kHz 7 100 kHz 8 200 kHz 9 300 kHz 10 400 kHz 11 500 kHz 12 ...
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Non-Multiplexed Microprocessor Port Timing Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS ...
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DS CS R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 23 - Motorola Non-Multiplexed Bus Timing ZL50052 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 56 Zarlink Semiconductor ...
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AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 ...
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TOP VIEW NOTES:- 1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement array c Zarlink Semiconductor 2003 All rights reserved. ...
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