ZL50062 ZARLINK [Zarlink Semiconductor Inc], ZL50062 Datasheet
ZL50062
Related parts for ZL50062
ZL50062 Summary of contents
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... Timing Unit C8i PLL V DD_PLL Figure 1 - ZL50062/4 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate ( 16Mbps), and 64 Inputs and 64 Outputs ...
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... I/O supply voltage • 5V tolerant inputs, outputs and I/Os Applications • Central Office Switches (Class 5) • Media Gateways • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers ZL50062/4 2 Zarlink Semiconductor Inc. Data Sheet ...
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... ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four different data rates, 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps. All 64 input and 64 output streams must operate at the same data rate ...
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... Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ZL50062/4 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Advancement Registers (LOAR0 to LOAR31 13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0 13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31 13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0 13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.8 Bit Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.9 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ZL50062/4 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50062/4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50064 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram (as viewed through top of package Figure 3 - ZL50062 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram (as viewed through top of package Figure 4 - 16,384 x 16,384 Channels (16Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - 8,192 x 8,192 Channels (16Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration ...
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... Table 20 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 21 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 22 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 24 - Bit Rate Register (BRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 ZL50062/4 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... BSTi22 BSTi21 254 BSTi23 BSTi24 256 Figure 2 - ZL50064 LQFP Connections (256 LQFP, 28mm x 28mm) Pin Diagram ZL50062/4 170 168 166 164 162 160 158 156 154 152 150 148 146 144 256 PIN LQFP (TOP VIEW) ...
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... BSTi11 VDD_IO N BSTi12 BSTi13 BSTi14 BSTi15 P BSTi17 BSTi18 BSTi19 BSTi20 R BSTi22 BSTi23 BSTi24 BSTi25 T BSTi27 BSTi28 BSTi29 BSTi30 Figure 3 - ZL50062 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram ZL50062 R/W CS IC_ IC_ IC_ OPEN OPEN OPEN A5 A6 ...
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... C8o 41 FP8o 42 C16o NA ZL50062/4 ZL50062 Package (256-ball PBGA) T10 Master Clock (5V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the ...
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... LSTi16-31 63, 62, 61, 59, 60, 57, 58, 55, 56, 53, 54, 51, 52, 46, 45, 44 ZL50062/4 ZL50062 Package (256-ball PBGA) P11 Frame Pulse Output (5V Tolerant Three-state Output). When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 61ns-wide frame pulse. When the FPW bit is HIGH, this pin outputs a 122ns-wide frame pulse ...
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... H2, H3, H4, 208, 210, J1, J2, J3, J4 215, 216, 217, 218, 219, 220, 221, 222 ZL50062/4 ZL50062 Package (256-ball PBGA) B10 Output Drive Enable (5V Tolerant Input with Internal Pull-up). An asynchronous input providing Output Enable control to the BSTo0-31 and LSTo0-31 outputs. When LOW, the BSTo0-31 and LSTo0-31 outputs are driven HIGH or high impedance (dependent on the BORS and LORS pin settings respectively) ...
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... N7, N6, P9, 25, 24, 19, P8, P7, P6, 18, 17, 15, R9, R8, R7, 16, 13, 14, 11 ZL50062/4 ZL50062 Package (256-ball PBGA) D12 Local Output Reset State (5V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the LSTo0-31 outputs driven high. Following initialization, the Local stream outputs are always active ...
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... TMS 147 TDi 145 TDo 146 ZL50062/4 ZL50062 Package (256-ball PBGA) A8 Chip Select (5V Tolerant Input). Active LOW input used by the microprocessor to enable the microprocessor port access. Note that a minimum of 30ns must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access ...
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... K11, L8, L9 190, 200, 201, 212, 213, 225, 226, 245, 246 ZL50062/4 ZL50062 Package (256-ball PBGA) D11 Test Reset (5V Tolerant Input with Internal Pull-up). Asynchronously initializes the JTAG TAP controller to the Test-Logic-Reset state. This pin must be pulsed LOW during power-up for JTAG testing ...
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... IC_GND 32, 33, 158, D6, D7, D8, 159, 160, 161 D9, T6, T7, ZL50062/4 ZL50062 Package (256-ball PBGA) M11 No Connects. These pins are not used and can be tied HIGH, LOW, or left unconnected. Internal Connections - OPEN. These pins must be left A12, A13, unconnected ...
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... This gives the maximum 16,384 x 16,384 channel capacity. Often a system design needs to differentiate between a Backplane and a Local side needs to put the switch in a bi-directional configuration. In this case, the ZL50062/64 can be used as shown in Figure 5 to give 8,192 x 8,192 channel bi-directional capacity. BSTi0-31 ...
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... Flexible Configuration The ZL50062/64 can be configured as a 16K by 16K non-blocking unidirectional digital switch non-blocking bi-directional digital switch blocking switch with various switching capacities. 1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) Because the input and output drivers are synchronous, the user can combine input Backplane streams and input Local streams as well as output Backplane streams and output Local streams to increase the total number of input and output streams of the switch in a unidirectional configuration, as shown in Figure 4 ...
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... Local Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection Memory. Refer to Section 8.1, Local Connection Memory, and Section 11.3, Local Connection Memory Bit Definition for more details. ZL50062/4 19 Zarlink Semiconductor Inc. Data Sheet ...
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... In addition, the ZL50062 device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to the output ports. The ZL50064 only provides FP8o and C8o outputs. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master frame pulse (FP8i) ...
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... BSTi/LSTi0- (8Mbps) GCI-Bus BSTi/LSTi0- (4Mbps) ST-BUS BSTi/LSTi0- (4Mbps) GCI-Bus BSTi/LSTi0-31 0 (2Mbps) ST-BUS BSTi/LSTi0-31 7 (2Mbps) GCI-Bus Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates ZL50062/4 Channel Channel Channel ...
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... Input Frame Pulse and Generated Frame Pulse Alignment The ZL50062 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. The ZL50064 only generates one frame pulse output, FP8o. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2 ...
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... Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50062/64, the input clock is 8.192MHz, and the jitter associated with this clock can have the highest frequency component at 4.096MHz. ...
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... Bit Delay = 1 Ch254 BSTi/LSTi0- Bit Delay = 7 1/2 Ch254 BSTi/LSTi0-31 Bit Delay = 7 3/4 2 Please refer to Control Register (Section 13.1) for SMPL_MODE definition. Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16Mbps ZL50062/4 Ch0 Bit Delay, 1/4 Ch0 ...
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... The Local and Backplane Output Advancement Registers, LOAR0 - LOAR31 and BOAR0 - BOAR31, are used to control the Local and Backplane output advancement respectively. The advancement is determined with reference to the internal system clock rate (131.072MHz). The advancement can cycles, -4 cycles or -6 cycles, which converts to approximately 0ns, -15ns, -31ns or -46ns as shown in Figure 11. ZL50062/4 Ch127 Ch0 0 ...
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... The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE. RESET ODE (input pin) (input pin Table 1 - Local and Backplane Output Enable Control Priority ZL50062/4 Bit Advancement, 0 Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -4 Ch255 Bit 0 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 ...
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... Table 3 describes the variable range for output streams. The data throughput delay under various input channel and output channel conditions can be summarized as frames + ( Table 2 - Variable Range for Input Streams Table 3 - Variable Range for Output Streams ZL50062/4 LE/BE OSB (Local / (Control ...
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... Frame Frame N Serial Input Data Frame N Data Serial Output Data Frame N-2 Data Figure 14 - Data Throughput Delay with Input Ch13 Switched to Output Ch0 ZL50062/4 Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + 0 ...
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... The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A delay of an additional 250 s must also be waited before the first microprocessor access is performed following the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format. ZL50062/4 supply (nominally +3.3V established before the DD_IO supplies (nominally +1 ...
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... The Control Register bits MS[2:0] must be set to 001 to select the Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 6.0, Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access. ZL50062/4 RESET de-assertion Figure 15 - Hardware RESET De-assertion 30 Zarlink Semiconductor Inc ...
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... The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the Block Programming Register or the MBP bit of the Control Register. Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a device reset, can be used. ZL50062/4 Source Stream No. Bits[12:8] legal values 0:31 ...
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... Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register. 10.0 JTAG Port The ZL50062/64 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. 10.1 Test Access Port (TAP) The Test Access Port (TAP) consists of four input pins and one output pin described as follows: • ...
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... The Bypass Register The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo. 10.2.2.3 The Device Identification Register The JTAG device ID for the ZL50062/64 is 0C38E14B Version, Bits <31:28>:0000 Part No., Bits <27:12>:1100 0011 1000 1110 Manufacturer ID, Bits <11:1>:0001 0100 101 Header, Bit < ...
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... Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-31) in place of data defined by the Source Control, Stream and Channel Address bits. ZL50062/4 Description Table 8 - Local Data Memory (LDM) Bits ...
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... When LOW, the channel is in Connection Mode (data to be output on channel originated in Backplane or Local Data Memory). When HIGH, the channel is in Message Mode (data to be output on channel originated in Backplane Connection Memory). Table 11 - BCM Bits for Source-to-Backplane Switching ZL50062/4 Description Description 35 Zarlink Semiconductor Inc. ...
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... Local Output Advancement Register 0 - 31, LOAR0 - 00A3 - 00C2 Backplane Output Advancement Register 0 - 31, BOAR0 - 014D Memory BIST Register, MBISTR H 1001 Bit Rate Register, BRR H 3FFF Device Identification Register, DIR H Table 12 - Address Map for Registers (A14 = 0) ZL50062/4 Description Register 36 Zarlink Semiconductor Inc. Data Sheet ...
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... Output Clock Polarity When LOW, the output clock has the same polarity as the input clock. When HIGH, the output clock is inverted. This applies to both the 8MHz (C8o) and 16MHz (C16o) output clocks. ZL50062/4 Description , the Frame Boundary Discriminator can handle both low B ...
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... Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 13 - Control Register Bits (continued) ZL50062/4 Description ODE Pin OSB bit BSTo0-31, LSTo0-31 ...
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... ZL50062/4 (a) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (c) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL ...
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... FP8i (g) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 17 - Frame Boundary Conditions, GCI-Bus Operation Zarlink Semiconductor Inc. ZL50062/4 Frame Boundary 40 Data Sheet ...
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... BPE 0 Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 s, upon completion of programming. Set LOW to abort the programming operation. Table 14 - Block Programming Register Bits ZL50062/4 Description 41 Zarlink Semiconductor Inc. Data Sheet ...
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... The LIDR0 to LIDR31 registers are configured as follows: LIDRn Bit Name (where 31) 15:5 Reserved 4:0 LID[4:0] Table 15 - Local Input Bit Delay Register (LIDRn) Bits ZL50062 bit. 4 Reset Description Value 0 Reserved Must be set to 0 for normal operation ...
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... Table 16 - Local Input Bit Delay and Sampling Point Programming Table ZL50062 bit periods forward, with resolution bit location -bit increments SMPL_MODE = LOW ...
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... Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be adjusted in 1-bit increments from bits. The BIDR0 to BIDR31 registers are configured as follows: BIDRn Bit Name (where 31) 15:5 Reserved 4:0 BID[4:0] Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits ZL50062/4 SMPL_MODE = LOW Input Data LID1 LID0 Bit Delay ...
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... Table 18 - Backplane Input Bit Delay and Sampling Point Programming Table ZL50062 bit periods forward, with resolution bit location -bit increments SMPL_MODE = LOW ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Local Output Advancement Clock Rate 131.072 MHz -2 cycles (~15ns) -4 cycles (~31ns) -6 cycles (~46ns) Table 20 - Local Output Advancement (LOAR) Programming Table ZL50062/4 SMPL_MODE = LOW Input Data BID1 BID0 Bit Delay 1 ...
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... The MBISTR register is configured as follows: Reset Bit Name Value Reserved 15:13 Reserved 0 Must be set to 0 for normal operation Table 23 - Memory BIST Register (MBISTR) Bits ZL50062/4 Reset Name Value Reserved 0 Reserved Must be set to 0 for normal operation BOA[1:0] 0 Backplane Output Advancement Value BOA1 ...
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... Local Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Local Connection Memory BIST sequence (indicated by assertion of BISTCCL). A HIGH indicates Pass, a LOW indicates Fail. Table 23 - Memory BIST Register (MBISTR) Bits (continued) ZL50062/4 Description 48 Zarlink Semiconductor Inc. Data Sheet ...
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... The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This register is read-only. The DIR register is configured as follows: Bit Name Reset Value 15:8 Reserved 7:4 RC[3:0] 3 Reserved 2:0 DID[2:0] Table 25 - Device Identification Register (DIR) Bits ZL50062/4 Description Bit 2 Bit 1 Bit Rate of all ST-BUS Streams Table 24 - Bit Rate Register (BRR) Bits ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Operating Temperature 2 Positive Supply 3 Positive Supply 4 Positive Supply 5 Input Voltage 6 Input Voltage on 5V Tolerant Inputs Voltages are with respect to ground (V ) unless otherwise stated. SS ZL50062/4 Symbol Min V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V ...
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... Output Low Voltage T 9 High impedance Leakage Output Pin Capacitance T S Voltages are with respect to ground (V ) unless otherwise stated. ss Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) ZL50062/4 Sym Min Typ Max I 4 DD_Core I 240 290 DD_Core I 100 ...
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... FP8o Output Delay (from output frame boundary to frame pulse edge) 13 C8o Clock Period 14 C8o Clock Pulse Width High 15 C8o Clock Pulse Width Low 16 C8o Clock Rise/Fall Time ZL50062/4 Sym Level Units V 0. DD_IO V 0. DD_IO V 0 ...
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... FP16o Output Delay (from output frame boundary to frame pulse edge) 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low 23 C16o Clock Rise/Fall Time ZL50062/4 Sym Min Typ t 117 122 OFPW16_122 OFPW16_61 t 58 ...
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... Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 18 - Input and Output Clock Timing Diagram for ST-BUS ZL50062/4 t IFPW244 t ...
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... Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 19 - Input and Output Clock Timing Diagram for GCI-Bus ZL50062/4 t IFPW244 t ...
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... Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point 2 Local/Backplane Serial Input Set-up Time 3 Local/Backplane Serial Input Hold Time 4 Output Frame Boundary Offset 5 Local/Backplane Serial Output Delay ZL50062/4 Sym Min Typ Max IDS16 IDS8 t 178 ...
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... CK_int * L/BSTo0-31 Bit1 Bit0 8.192Mbps Ch127 Ch127 L/BSTo0-31 Bit0 4.096Mbps Ch63 L/BSTo0-31 Bit0 2.048Mbps Ch31 Note *: CK_int is the internal clock signal of 131.072MHz Figure 20 - ST-BUS Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) ZL50062/4 t IDS8 t SIS8 t SIH8 IDS4 t SIS4 t SIH4 Bit7 ...
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... FP8i C8i CK_int * L/BSTi0-31 Bit1 16.384Mbps Ch255 FP8o C8o CK_int * L/BSTo0-31 Ch255 16.384Mbps Note *: CK_int is the internal clock signal of 131.072MHz Figure 21 - ST-BUS Local/Backplane Data Timing Diagram (16Mbps) ZL50062/4 t IDS16 t SIS16 t SIH16 Bit7 Bit0 Ch0 Ch255 t OFBOS t SOD16 Bit0 Bit7 Ch0 58 Zarlink Semiconductor Inc. ...
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... CK_int * L/BSTo0-31 Bit6 Bit7 Ch127 Ch127 8.192Mbps L/BSTo0-31 Bit7 Ch63 4.096Mbps L/BSTo0-31 Bit7 2.048Mbps Ch31 Note *: CK_int is the internal clock signal of 131.072MHz Figure 22 - GCI-Bus Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) ZL50062/4 t IDS8 t SIS8 t SIH8 IDS4 t SIS4 t SIH4 Bit0 ...
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... C8i CK_int * L/BSTi0-31 Bit6 Bit7 16.384Mbps Ch255 Ch255 FP8o C8o CK_int * L/BSTo0-31 Bit7 Ch255 16.384Mbps Note *: CK_int is the internal clock signal of 131.072MHz Figure 23 - GCI-Bus Local/Backplane Data Timing Diagram (16Mbps) ZL50062/4 t IDS16 t SIS16 t SIH16 Bit0 Bit1 Ch0 Ch0 t OFBOS t SOD16 Bit0 Bit1 ...
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... Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to high impedance Note 1: High Impedance is measured by pulling to the appropriate rail with CLK STo STo Figure 24 - Serial Output and External Control ODE ZL50062/4 Sym Min Typ Max ...
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... Input Clock Jitter Tolerance Jitter Frequency 1 1kHz 2 10kHz 3 50kHz 4 66kHz 5 83kHz 6 95kHz 7 100kHz 8 200kHz 9 300kHz 10 400kHz 11 500kHz 12 1MHz 13 2MHz 14 4MHz ZL50062/4 16.384Mbps Data Rate Units Jitter Tolerance 1200 ns 1200 ns 150 ns 110 ...
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... Note 2: There must be a minimum of 30ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum of 30ns must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access). ZL50062/4 Sym Min Typ Max t 0 CSS ...
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... DS CS R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 26 - Motorola Non-Multiplexed Bus Timing ZL50062/4 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 64 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH RDH V TT ...
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... TDo Output Delay 9 TRST pulse width † Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST Figure 27 - JTAG Test Port Timing Diagram ZL50062/4 Sym Min Typ t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...