ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet - Page 13

• Manufacturer Part Number: ZL50073GAG2
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
B18, E15
C16
D14
C15
D15
A19
B17
Pin
C5
SIZ0-1
BERR
Name
WAIT
R/W
DTA
CS
DS
IM
Zarlink Semiconductor Inc.
Chip Select Input (5 V Tolerant Input)
Active low input used with DS to enable read and write access to
the ZL50073.
Data Strobe Input (5 V Tolerant Input)
Active low input used with CS to enable read and write access to
the ZL50073.
Read/Write Input (5 V Tolerant Input)
This input controls the direction of the data bus lines (D31 - 0)
during a microprocessor access. This pin is set high and low for the
read and write access respectively.
Data Transfer Acknowledge (5 V Tolerant, 3.3 V Tri-state
Output with Slew-Rate)
This active low output indicates that a data bus transfer is
complete. Usually used with a Motorola interface. An external
pull-up resistor is required to hold this pin HIGH when output is
high-impedance.
Transfer Bus Error Output with Slew Rate Control (5 V
Tolerant, 3.3 V Tri-state Outputs with Slew-Rate Control)
This pin goes low whenever the microprocessor attempts to access
an invalid memory space inside the device. In Motorola bus mode,
if this bus error signal is activated, the data transfer acknowledge
signal, DTA, will not be generated. In Intel bus mode, the
generation of the DTA is not affected by this BERR signal. An
external pull-up resistor is required to hold a HIGH level when
output is high-impedance.
Data Transfer Wait Output (5 V Tolerant, 3.3 V Tri-state Output
with Slew Rate)
Active low wait signal output. It indicates that a data bus transfer is
complete when it goes from low to high. Usually used with an Intel
interface. An external pull-up resistor is required to hold this pin
HIGH when output is high-impedance
Data Transfer Size/Upper and Lower Data Strobe Inputs (5 V
Tolerant Inputs)
Motorola 32-bit mode - signals indicate data transfer size, refer to
Section 10.0.
Motorola 16-bit mode:SIZ0 - LDS, SIZ1 - UDS.
Active low upper and lower data strobes, UDS and LDS, indicate
whether the upper byte, D15 - 8, and/or lower byte, D7 - 0, is being
accessed.
Intel 32/16-bit mode: SIZ0 - BE0, SIZ1 - BE1.
Active low Intel type bus-enable signals, BE1 and BE0
Microprocessor Port Bus Mode Select (5 V Tolerant Input)
Control input:
0 = Motorola mode
1 = Intel mode
ZL50073
13
Description
Data Sheet