ZL50074GAC ZARLINK [Zarlink Semiconductor Inc], ZL50074GAC Datasheet
ZL50074GAC
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ZL50074GAC Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved Channel TDM Switch with 128 Input and 128 Output Streams ZL50074GAC ZL50074GAG2 **Pb Free Tin/Silver/Copper • Control interface compatible with Intel and ...
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Digital Loop Carriers • Time Division Multiplexers • Media Gateways Description The ZL50074 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The device can switch 64 kbps or Nx64 kbps TDM channels from ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50074 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Data Rate and Maximum Switch Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Change Summary The following table captures the changes from the April 2005 issue. Page Item 24 8.4.1, “Read Cycle“ 25 Figure 6 "Read Cycle Operation" 25 8.4.2, “Write Cycle“ 26 Figure 7 "Write Cycle Operation" The following table captures the ...
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Pin Diagram - ZL50074 484 Ball PBGA (as viewed through top of package) A1 corner identified by metallized marking CKo STiA D[30] D[25] D[20] D[16] D[15] D[11] [0] ...
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Pin Description Pin Name F7, F10, F13, F17, G9, G12, V DD_CORE G15, H6, H10, H13, H16, J7, K8, K15, K17, L6, L16, M7, N8, N15, P6, P16, P17, R7, R10, R13, T9, T12, T15, U10, U13, U17 F9, F12, ...
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Pin Description (continued) Pin Name D6, F5, E3, D1, J3, L5, M3, STiC0-31 M4, U1, U3, AA1, AA2, V7, W8, AB6, V10, AB11, Y14, AB18, U16, AB21, W20, U20, P19, R22, N22, L18, H21, G20, F20, D20, E16 C4, B2, ...
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Pin Description (continued) Pin Name D4, F4, G3, G2, G1, L2, N3, SToD0-31 T1, U2, T6, V5, AA3, W7, AA7, W10, Y11, Y12, AB17, AA18, W18, V19, AA22, U21, N17, P22, L21, L17, H20, D22, E20, C20, D16 W12 AA13 ...
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Pin Description (continued) Pin Name A1, AB4, R18, E14 CKo0-3 G5, Y6, T19, C17 FPo0-3 W15, V14 CK_SEL0-1 Master Clock Input Select (5 V Tolerant Inputs) L1 A18, J21, M22, R3, V13, W13, Y13, AA16, AA17 AB13, AB14 A11, C11, ...
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Pin Description (continued) Pin Name D14 C15 A19 B17 BERR D15 B18, E15 SIZ0 ZL50074 DS Data Strobe Input (5 V Tolerant Input) Active low input used with CS to enable read and write access to the ZL50074. ...
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Pin Description (continued) Pin Name A20 D18 B21 A22 C19 E17 1.0 Functional Description 1.1 Overview The device has 128 ST-BUS/GCI-Bus inputs (STiA0 - 31, STiB0 - 31, STiC0 - 31, STiD0 - 31) and 128 ST-BUS/GCI-Bus outputs (SToA0 - ...
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The ZL50074 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams. The rate of the input clock is defined by ...
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Table 1 shows the maximum number of streams available at different bit rates. The ZL50074 deactivates unused streams when operating at the higher bit rates as shown in Table 2. Input or Output Group 31) ...
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When the internal system clock is not used as the clock source, there are limitations to the data rate and the output clock rate. For all the input and output stream groups that do not use the internal system clock ...
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Nominal Channel n Boundary STi[ 00000 (Default) 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Example: With a setting of 01111 the sampling point for bit 7 will be 3 ...
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Nominal 8 MHz Clock Nominal 16 MHz Clock Nominal 32/65 MHz Clock Nominal Output Bit Timing OSBA = 00 Level 1 Advance OSBA = 01 Level 2 Advance OSBA = 10 Level 3 Advance OSBA = 11 This programming feature ...
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To increase programming bandwidth, the ZL50074 has separate addressable 32 bit memory locations, called Connection Memory Least Significant Bytes (LSB), which provide direct access to the Connection Memories’ Lowest data bytes (bits four consecutive message ...
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N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N = Last Channel Figure 4 - Data Throughput Delay for Constant Delay 7.2 Variable Delay ...
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Microprocessor Port The ZL50074 has a generic microprocessor port that provides access to the internal Data Memory (read access only), Connection Memory and Control Registers. The port size can be configured to be either 32 bit or 16 bit, ...
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For example, to transfer all 32 bits in a single access SIZ1 = 0, SIZ0 = 0. To transfer D15 - 8 only SIZ1 = 0, SIZ0 = ...
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Bit Bus Operation In 16 bit mode (D16B = 1), D15 - 0 are used for data transfers to/from the ZL50074. D31 - 16 are unused and must be connected to a defined logic level. D15 on the ...
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Address Register (Hex) Description 40200 or Group Control Register (Group 0) 40201 40282 or Input Clock Control Register 40283 40286 or Output Clock Control Register 40287 40284 or Output Clock Control Register 40285 Table Bit Mode Example ...
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Address A, SIZ1 - 0 CS R/W DS Hi-Z Data Hi-Z DTA BERR Hi-Z WAIT The cycle termination signals WAIT & DTA are provided for all bus configurations. 8.4.2 Write Cycle The operation of the write cycle is illustrated in ...
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Address SIZ1 - 0 CS R/W DS Data DTA Hi-Z BERR WAIT Hi-Z The cycle termination signals WAIT & DTA are provided for all bus configurations. 9.0 Power-up and Initialization of the ZL50074 9.1 Device Reset and Initialization The PWR ...
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Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes approximately 1ms for the internal initialization to complete • Automatic block initialization of the Connection Memory to all zeros occurs, without ...
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Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDo is ...
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Memory Map of ZL50074 The memory map for the ZL50074 is given in Table 11. Address (Hex) 00000 - 1FFFF Connection Memory 20000 - 27FFF Connection Memory LSB 28000 - 2FFFF Data Memory: Read only; Bus error on write ...
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Start Output Address Group (Hex) 0 000000 1 001000 2 002000 3 003000 4 004000 5 005000 6 006000 7 007000 8 008000 9 009000 10 00A000 11 00B000 12 00C000 13 00D000 14 00E000 15 00F000 Table 12 - ...
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The address range for a particular stream is given by adding the group start address, as indicated in Table 12, to the appropriate stream offset range, as indicated in Table 13. For example, the Connection Memory address range for SToB12 ...
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Connection Memory Bit Functions The bit functions of the connection memory are illustrated in Table 15. External Read/Write Address: 000000 H Reset Value: 0000 PCF PCF PCF ...
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Connection Memory LSB The Connection Memory Least Significant Byte field is provided to give a convenient alternative way to modify the output data for a stream in message mode. In this memory address range, all of the connection memory ...
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Device Data Rate Timeslot Range 65 Mbps 32 Mbps 16 Mbps 8 Mbps Table 17 - Connection Memory LSB Stream Address Offset at Various Output Rates Within each stream group, the mapping of each of the actual output streams, SToAn, ...
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Start Input Address Group (Hex) 12 02B000 13 02B400 14 02B800 15 02BC00 Table 18 - Data Memory Group Address Mapping (continued) Within each stream group, the mapping of each of the actual input streams, STiAn, STiBn, STiCn and STiDn, ...
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Group Control Registers The ZL50074 addresses the issues of a simple programming model and automatic stream configuration by defining a basic switching bit rate of 65.536 Mbps and by grouping the I/O streams. Each TDM I/O group contains 4 ...
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External Read/Write Address: 40200 - 4027F H Reset Value: 000C000C Bit Name ...
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External Read/Write Address: 40200 - 4027F H Reset Value: 000C000C Bit Name ...
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Input Clock Control Register The Input Clock Control Register is used to select the logic sense of the input clock. External Read/Write Address: 40280 H Reset Value: 0DB ...
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Output Clock Control Register The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output clocks. The bit functions of the Output Clock Control Register are illustrated in Table 23. External ...
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External Read/Write Address: 40284 H Reset Value: 060D1C3C GCO SEL3 POL3 CKO2 CKO2 GCO FPO CKO CKO1 SRC1 SRC0 SEL1 POL1 POL1 RATE1 Bit Name ...
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External Read/Write Address: 40284 H Reset Value: 060D1C3C GCO FPO SEL3 POL3 CKO2 CKO2 GCO FPO CKO CKO1 SRC1 SRC0 SEL1 POL1 POL1 RATE1 Bit ...
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External Read/Write Address: 40284 H Reset Value: 060D1C3C GCO FPO SEL3 POL3 CKO2 CKO2 GCO FPO CKO CKO1 SRC1 SRC0 SEL1 POL1 POL1 RATE1 Bit ...
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Block Init Register The Block Init Register bit read/write register at address 040288 - 04028B The Block Init Register is used during block initialization of the connection memory. A block initialization automatically occurs at power-up. However, ...
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Global Rate Control Register The Global Rate Control Register is used to select the data rate of all the input and output streams. On power-up, the GBR bits are both reset to 0, corresponding to a rate of 8.192 ...
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DC/AC Electrical Characteristics 1 Absolute Maximum Ratings - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics 1 Chip I/O Supply Voltage 2 Chip Core Supply Voltage 3 Input Voltage (non-5 V tolerant inputs) 4 Input Voltage ...
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DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 2 1 Core Supply Current 2 I/O Supply Current 3 Leakage Current 4 Dynamic Power Dissipation 5 Input High Voltage 6 Input Low Voltage 7 ...
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AC Electrical Characteristics - FPi0-2 and CKi0-2 Timing No. Characteristic (Figure ) 1 FPi0-2 Input Frame Pulse Setup Time 2 FPi0-2 Input Frame Pulse Hold Time 3 FPi0-2 Input Frame Pulse width 4 CKi0-2 Input Clock Period (average value, ...
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FPi t CKi Input Frame Boundary Figure 8 - Frame Pulse Input and Clock Input 1 AC Electrical Characteristics - FPi and CKi Skew No. Characteristic (Figure 9) 1 CKi0 to CKi1, 2 Skew 1. Characteristics are over recommended operating ...
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AC Electrical Characteristics - FPO0-3 and CKO0-3 (65.536 MHz) Timing No. Characteristic 1 FPO0-3 Output Frame Pulse Setup Time 2 FPO0-3 Output Frame Pulse Hold Time 3 CKO0-3 Output Clock Period 1 AC Electrical Characteristics - FPO0-3 and CKO0-3 ...
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FPo0-3 t FPOS CKo0-3 Output Frame Boundary Figure 10 - ST-Bus Frame Pulse and Clock Output Timing FPo0-3 t FPOS CKo0-3 Output Frame Boundary Figure 11 - GCI Frame Pulse and Clock Output Timing AC Electrical Characteristics - Output Clock ...
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AC Electrical Characteristics - Serial Data Timing No. Characteristic (Figure 12) 1 CKi to CKo Positive edge Propagation Delay 2 CKi to CKo Negative edge Propagation Delay 3 STi to posedge CKi setup 4 STi to posedge CKi hold ...
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FPi (negative sense) CKo (negative sense) CKi (negative sense) STin STon STon ODE FPi (negative sense) CKo (positive sense) CKi (positive sense) STin STon STon Note 1: CKi frequency is assumed to be twice of the STin data rate, so ...
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AC Electrical Characteristics - Serial Data Timing No. Characteristic (Figure ) 1 STi to posedge CKo setup 2 STi to posedge CKo hold 3 STi to negedge CKo setup 4 STi to negedge CKo hold 5 Posedge CKo to Output ...
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FPo (negative sense) CKo (negative sense) STin STon STon FPo (negative sense) CKo (positive sense) STin STon STon Note 1: CKo frequency is assumed to be twice of the STin data rate, so that the sampling point is at the ...
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AC Electrical Characteristics - CKo to Other CKo No. Characteristic (Figure 12) 1 CKo1 to CKo0 skew 2 CKo2 to CKo0 skew 3 CKo1 to CKo3 skew 4 CKo2 to CKo3 skew 5 CKo3 to CKo0 skew 6 CKo2 to ...
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AC Electrical Characteristics - Microprocessor Bus Interface No Characteristics (Figure , & Figure 16 Recovery 2 CS Recovery 3 CS asserted setup to DS asserted 4 Address, SIZ0-1, R/W setup to DS asserted 5 CS hold from DS ...
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DS t CSRE CS A18-A0 RWN,SIZ D31-D0 READ D31-D0 WRITE Hi-Z DTA BERR Hi-Z WAIT Figure 15 - Microprocessor Bus Interface Timing DS SIZ1-SIZ0 (BE1-BE0 or UDS, LDS) Figure 16 - Intel Mode Timing ZL50074 t DSRE t CSS t ...
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AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing No. Characteristic (Figure 17) 1 TCK Clock Period 2 TCK Clock Frequency 3 TCK Clock Pulse Width High 4 TCK Clock Pulse Width Low 5 TMS Set-up Time ...
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