ZL50130PBGA ZARLINK [Zarlink Semiconductor Inc], ZL50130PBGA Datasheet
ZL50130PBGA
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ZL50130PBGA Summary of contents
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Applications • Ethernet Pseudo-Wires across a Packet Switch Network Features Ethernet Pseudo-Wire Emulation Functions Supports the following functions for Ethernet Pseudo- Wire emulation over the packet domain: • Transports the complete Ethernet frame (less preamble and FCS) across the PSN ...
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Description The ZL50130 is part of a range of highly functional bridging devices. It provides the capability to extend a Local Area Network based on Ethernet across a service provider’s packet switched network. This allows a company with multiple sites ...
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Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Changes Summary The following table captures the changes from the September 2004 issue. Page Item 10, 11 Figure 5 and Ball Signal Assignment Table 41 8.0 DC Characteristics Table and Output Levels Table 38 Section 4.8 10 Figure 5 ...
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Basic Operation A diagram of the ZL50130 device is given in Figure 4, which shows the major data flows between functional components. Provider Edge Interworking Function Ethernet Phy Switch Phy Phy e.g. MVTX2604 Phy MVTX2804 Phy Phy aggregation and ...
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CE-Bound Flow The flow in the reverse direction is essentially similar to the PSN-bound flow. Packets from the PSN are received by its PSN-facing MAC interface. Valid packets are passed to the Packet Classifier to determine the destination. Once ...
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ZL50130 Package view from TOP side. Note that ball A1 is non-chamfered corner ...
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Ball Signal Assignment Ball Signal Name Number A1 GND A2 N/C A3 N/C A4 N/C A5 N/C A6 N/C A7 N/C A8 N/C A9 N/C A10 N/C A11 N/C A12 N/C A13 GND A14 N/C A15 N/C A16 N/C A17 ...
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Ball Signal Name Number D24 N/C D25 N/C D26 N/C E1 RAM_DATA[10] E2 RAM_DATA[9] E3 RAM_DATA[5] E4 RAM_DATA[4] E5 RAM_DATA[2] E6 N/C E7 N/C E8 N/C E9 N/C E10 N/C E11 N/C E12 N/C E13 N/C E14 N/C E15 N/C ...
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Ball Signal Name Number K2 RAM_PARITY[0] K3 RAM_DATA[31] K4 RAM_DATA[30] K5 GND K6 VDD_CORE K9 VDD_IO K18 VDD_IO K21 VDD_CORE K22 GND K23 M3_TXD[3] K24 M3_TXEN K25 M3_TXER K26 M3_RXCLK L1 RAM_PARITY[7] L2 RAM_PARITY[6] L3 RAM_PARITY[5] L4 RAM_PARITY[4] L5 RAM_PARITY[3] ...
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Ball Signal Name Number R13 GND R14 GND R15 GND R16 GND R18 VDD_IO R21 M1_TXD[0] R22 M1_TXD[3] R23 N/C R24 N/C R25 M1_COL R26 M1_RXD[1] T1 RAM_ADDR[17] T2 RAM_ADDR[18] T3 RAM_BW_B T4 IC_GND T5 GND T6 A1VDD T9 VDD_IO ...
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Ball Signal Name Number AA12 CPU_ADDR[12] AA13 VDD_CORE AA14 VDD_CORE AA15 CPU_DATA[8] AA16 CPU_DATA[15] AA17 CPU_DATA[23] AA18 VDD_CORE AA19 M2_RXCLK AA20 M2_RXDV AA21 GND AA22 M0_TXD[0] AA23 M0_TXD[3] AA24 M0_REFCLK AA25 N/C AA26 M0_RXD[0] AB1 GPIO[5] AB2 GPIO[11] AB3 GPIO[14] ...
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Ball Signal Name Number AE10 CPU_ADDR[8] AE11 CPU_ADDR[13] AE12 CPU_ADDR[18] AE13 CPU_ADDR[20] AE14 CPU_OE AE15 CPU_TS_ALE AE16 CPU_DREQ1 AE17 IC AE18 CPU_DATA[4] AE19 CPU_DATA[9] AE20 CPU_DATA[13] AE21 CPU_DATA[18] AE22 CPU_DATA[25] AE23 CPU_DATA[28] AE24 M2_TXD[0] AE25 M2_TXD[3] AE26 M2_COL AF1 GND ...
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Functional Block Descriptions 3.1 Task Manager Conceptually, the task manager performs the function of a router in the centre of the chip, directing packets to the appropriate processing blocks. The architecture is based on the task-oriented approach derived from ...
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Features include: • bytes of higher layer protocol headers (layers • Specific support for the following protocols: • UDP (RFC 768) • L2TP versions 2 and 3 (RFC 2661, draft-ietf-l2tpext-l2tp-base-02) • Ethernet PW (draft-ietf-pwe3-ethernet-encap) ...
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Packet Classification The ZL50130 contains an extremely flexible packet classifier, capable of operating on layers and identifying 272 separate flows. For instance, it can identify a separate data and control flow for each context, and a ...
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Once the class has been determined, a template is applied, extracting bits from any field in the first 96 bytes. These are used to determine the individual flow. For example, this could be used to check the ...
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RFC 2819 Remote Network Monitoring MIB (for SMIv2) • RFC 2863 Interfaces Group MIB 3.6 Memory Management Unit The Memory Management Unit handles all access to the on- and off-chip packet memory, arbitrating between the different modules requiring access. ...
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Table illustrates the maximum bandwidths achievable by an external DMA master. DMA Path ZL50130 to CPU only ZL50130 to CPU only CPU to ZL50130 only CPU to ZL50130 only Combined Combined Note 1: Maximum bandwidths are the maximum the ZL50130 ...
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Signal I/O M_MDC O H23 M_MDIO ID/ G26 OT Table 2 - MII Management Interface Package Ball Definition Signal I/O M0_LINKUP_LED O AB23 M0_ACTIVE_LED O AC26 M0_REFCLK I D AA24 M0_RXCLK I U AB22 M0_COL I D Y25 Table 3 ...
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Signal I/O M0_RXD[3: [3] [2] [1] [0] M0_RXDV I D V25 M0_RXER I D V26 M0_CRS I D U25 M0_TXCLK I U U24 M0_TXD[3:0] O [3] [2] [1] [0] M0_TXEN O V23 Table 3 - MII Port 0 ...
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Signal I/O M0_TXER O V22 Table 3 - MII Port 0 Interface Package Ball Definition Signal I/O M1_LINKUP_LED O F26 M1_ACTIVE_LED O AB25 M1_REFCLK I D M22 M1_RXCLK I U M23 M1_COL I D R25 M1_RXD[3: [3] [2] ...
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Signal I/O M1_RXDV I D M26 M1_RXER I D L21 M1_CRS I D L23 M1_TXCLK I U L22 M1_TXD[3:0] O [3] [2] [1] [0] M1_TXEN O P23 Table 4 - MII Port 1 Interface Package Ball Definition ZL50130 MII Port ...
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Signal I/O M1_TXER O N23 Table 4 - MII Port 1 Interface Package Ball Definition Note: This port must not be used to receive data at the same time as port 3, Signal I/O M2_LINKUP_LED O G23 M2_ACTIVE_LED O AB24 ...
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Note: This port must not be used to receive data at the same time as port 3, Signal I/O M2_RXER I D AC24 M2_CRS I D AC25 M2_TXCLK I U AD26 M2_TXD[3:0] O [3] [2] M2_TXEN O AC22 M2_TXER O ...
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Note: This port must not be used to receive data at the same time as port 2, Signal I/O M3_LINKUP_LED O G24 M3_ACTIVE_LED O AB26 M3_RXCLK I U K26 M3_COL I D J26 M3_RXD[3: [3] [2] M3_RXDV I ...
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Note: This port must not be used to receive data at the same time as port 2, Signal I/O M3_TXCLK I U H25 M3_TXD[3:0] O [3] [2] M3_TXEN O K24 M3_TXER O K25 Table 6 - MII Port 3 Interface ...
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External Memory Interface All External Memory Interface signals are 5 V tolerant. All External Memory Interface outputs are high impedance while System Reset is LOW. If the External Memory Interface is unused, all input pins may be left unconnected. ...
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Signal I/O RAM_ADDR[19:0] O [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] RAM_BW_A RAM_BW_B RAM_BW_C RAM_BW_D RAM_BW_E RAM_BW_F RAM_BW_G Table 7 - External Memory ...
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Signal I/O RAM_BW_H RAM_RW Table 7 - External Memory Interface Package Ball Definition 4.3 CPU Interface All CPU Interface signals are 5 V tolerant. All CPU Interface outputs are high impedance while System Reset is LOW ...
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Signal I/O CPU_CS I U AF14 CPU_WE I AD14 CPU_OE I AE14 CPU_TS_ALE I AE15 CPU_SDACK1 I AF15 CPU_SDACK2 I AD15 Table 8 - CPU Interface Package Ball Definition ZL50130 Package Balls CPU Chip Select. Synchronous to rising edge of ...
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Signal I/O CPU_CLK I AC14 CPU_TA OT AB14 CPU_DREQ0 OT AC15 CPU_DREQ1 OT AE16 CPU_IREQO O AF17 CPU_IREQ1 O AD16 Table 8 - CPU Interface Package Ball Definition ZL50130 Package Balls CPU PowerQUICC™ II Bus Interface clock input. 66 MHz ...
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System Function Interface All System Function Interface signals are 5 V tolerant. The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to allow the PLL’s to lock. Signal I/O ...
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JTAG Interface All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001). Signal I/O JTAG_TRST I U AE7 JTAG_TCK I AD8 JTAG_TMS I U AA10 JTAG_TDI I U AF7 JTAG_TDO O AC9 Table ...
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Power and Ground Connections Signal VDD_IO J9 J13 J17 V11 V15 GND A1 F6 L11 L15 M13 N1 N13 N22 P12 P16 R13 T5 T14 AA6 AF13 VDD_CORE F7 F20 AA13 A1VDD ...
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Miscellaneous 5.1 JTAG Interface and Board Level Test Features. The JTAG interface is used to access the boundary scan logic for board level production testing. 5.2 External Component Requirements • Direct connection to PowerQUICC™ II (MPC8260) host processor and ...
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Test Mode Control The System Test Mode is selected using the dedicated device input bus test_mode[2:0] as follows in Table 15. SYS_NORMAL_MODE SYS_TRI_STATE_MODE 7.3 System Normal Mode Selected by test_mode[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs ...
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DC Characteristics 8.1 Absolute Maximum Ratings* Parameter I/O Supply Voltage Core Supply Voltage PLL Supply Voltage Input Voltage Input Voltage (5 V tolerant inputs) Continuous current at digital inputs Continuous current at digital outputs Package power dissipation Storage Temperature ...
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DC Characteristics Characteristics Input Leakage Output (High impedance) Leakage Input Capacitance Output Capacitance Pullup Current Pullup Current tolerant inputs Pulldown Current Pulldown Current tolerant inputs Core 1.8 V supply current PLL 1.8 V supply current ...
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AC Characteristics 9.1 Packet Interface Timing Data for the MII packet switching is based on Specification IEEE Std. 802.3 - 2000. 9.1.1 MII Transmit Timing Parameter TXCLK period TXCLK high time TXCLK low time TXCLK rise time TXCLK fall ...
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MII Receive Timing Parameter RXCLK period RXCLK high wide time RXCLK low wide time RXCLK rise time RXCLK fall time RXD[3:0] setup time (RXCLK rising edge) RXD[3:0] hold time (RXCLK rising edge) RXDV input setup time (RXCLK rising edge) ...
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Management Interface Timing The management interface is common for all inputs and consists of a serial data I/O line and a clock line. Parameter M_MDC Clock Output period M_MDC high M_MDC low M_MDC rise time M_MDC fall time M_MDIO ...
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External Memory Interface Timing The timings for the External Memory Interface are based on the requirements of a ZBT-SRAM device, with the system clock speed at 100 MHz. Parameter RAM_DATA[63:0] Output Valid Delay RAM_RW/RAM_ADDR[19:0] Delay RAM_BW[7:0]# Delay RAM_DATA[63:0] Setup ...
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CPU Interface Timing Parameter CPU_CLK Period CPU_CLK High Time CPU_CLK Low Time CPU_CLK Rise Time CPU_CLK Fall Time CPU_ADDR[23:2] Setup Time CPU_ADDR[23:2] Hold Time CPU_DATA[31:0] Setup Time CPU_DATA[31:0] Hold Time CPU_CS Setup Time CPU_CS Hold Time CPU_WE/CPU_OE Setup Time ...
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The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of CPU_TA, not at the positive clock edge during the assertion of CPU_TA. CPU_CLK t CAS CPU_ADDR[23:2] t CSS CPU_CS CPU_OE CPU_WE CPU_TS_ALE ...
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CPU_CLK t CWV CPU_DREQ1 CPU_SDACK2 CPU_CS CPU_OE CPU_WE CPU_TS_ALE CPU_DATA[31:0] CPU_TA NOTE: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid when CPU_TA is asserted (always timed as shown). CPU_DATA ...
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System Function Port Parameter SYSTEM_CLK Frequency SYSTEM_CLK accuracy (synchronous master mode) SYSTEM_CLK accuracy (synchronous slave mode and asynchronous mode) Note 1: The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for ...
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JTAG Interface Timing Parameter JTAG_CLK period JTAG_CLK clock pulse width JTAG_CLK rise and fall time JTAG_TRST setup time JTAG_TRST assert time Input data setup time Input Data hold time JTAG_CLK to Output data valid JTAG_CLK to Output data high ...
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HIGH JTAG_TCK t TPH t TPSU JTAG_TMS JTAG_TDI Don't Care JTAG_TDO HiZ Figure 16 - JTAG Signal Timing JTAG_TCK JTAG_TRST Figure 17 - JTAG Clock and Reset Timing ZL50130 t LOW t JCP t TPSU t TOPDV t t ...
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Power Up sequence To power up the ZL50130 the following procedure must be used: • The Core supply must never exceed the I/O supply by more than 0.5 V • Both the Core supply and the I/O supply must ...
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Design and Layout Guidelines This guide will provide information and guidance for PCB layouts when using the ZL50130. Specific areas of guidance are: • High Speed Clock and Data, Outputs and Inputs • CPU_TA Output 11.1 High Speed Clock ...
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MAC Interface - special considerations during layout The MII interface passes data to and from the ZL50130 with their related transmit and receive clocks therefore recommended that the trace lengths for transmit related signals and their clock ...
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The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be fitted to ensure correct operation of the TA input to the processor recommended that the logic ...
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Reference Documents 13.1 External Standards/Specifications • IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture • IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer • MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification ...
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Glossary CONTEXT A programmed connection representing a unique packet stream. CPU Central Processing Unit DMA Direct Memory Access IETF Internet Engineering Task Force IP Internet Protocol (version 4, RFC 791, version 6, RFC 2460) JTAG Joint Test Algorithms Group ...
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Zarlink Semiconductor 2003 All rights reserved ISSUE 213837 ACN DATE 12Dec02 19Aug03 APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...