SY89840UMG Micrel Inc, SY89840UMG Datasheet - Page 4

• Manufacturer Part Number: SY89840UMG
• Description: IC MUX 2:1 LVPECL DIFF 16MLF
• Manufacturer: Micrel Inc
• Series: SY89r
• Type: Multiplexerr

Specifications of SY89840UMG

• Circuit: 1 x 2:1
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-MLF®, QFN
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: MLF
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/PECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 576-1434

February 2005
Pin Description
Truth Table
Pin Number
5, 8, 12
16, 13
3, 15
2, 14
4, 1,
6, 7
10
11
9
Exposed Pad
VREF-AC0
VREF-AC1
Pin Name
IN0, /IN0,
VT0, VT1
IN1, /IN1
Q, /Q
GND
VCC
CAP
SEL
IN0
X
X
0
1
/IN0
X
X
1
0
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC or DC-coupled signals as small as 100mV
(200mV
Please refer to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network
for maximum interface flexibility. See the “Input Interface Applications” section for
more details.
Reference Voltage: This output biases to V
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass
with 0.01µF low ESR capacitor to V
Due to the limited drive capability, the VREF-AC pin is only intended to drive its
respective VT pin. See “Input Interface Applications” section.
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor
and will default to a logic HIGH state if left open.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close
to VCC pins as possible.
Differential Outputs: This differential LVPECL output is a logic function of the IN0,
IN1, and SEL inputs. Please refer to the truth table below for details.
Ground: Ground pin and exposed pad must be connected to the same ground
plane.
Power-On Reset (POR) Initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to V
internal RPE logic starts up in a known state. See "Power-On Reset (POR)
Description" section for more details regarding capacitor selection. If this pin is
tied directly to V
function as a normal multiplexer. The CAP pin should never be left open.
INPUTS
IN1
pp
X
X
0
1
). Each pin of a pair internally terminates to a VT pin through 50Ω.
CC
/IN1
, the RPE function will be disabled and the multiplexer will
X
X
1
0
4
SEL
0
0
1
1
CC
Q
OUTPUTS
0
1
0
1
. Maximum sink/source current is ±1.5mA.
CC
[e-mail]
–1.2V. It is used for AC-coupling
/Q
1
0
1
0
CC
. The purpose is to ensure the
or [phone]
M9999-021705