IDT72V70840DA IDT, Integrated Device Technology Inc, IDT72V70840DA Datasheet - Page 3

• Manufacturer Part Number: IDT72V70840DA
• Description: IC DGTL SW 4096X4096 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70840DA

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V70840DA

IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
CLK
SYMBOL
GND
V
TX0-31
RX0-31
F0i
FE/HCLK Frame Evaluation/
TMS
TDI
TDO
TCK
TRST
RESET
WFPS
DS
R/W
CS
A0-13
D0-15
DTA
ODE
CC
HCLK Clock
Clock
Ground.
V
TX Output 0 to 31
(Three-state Outputs)
RX Input 0 to 31
Frame Pulse
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
Device Reset
(Schmitt Trigger Input)
Wide Frame Pulse Select
Data Strobe
Read/Write
Chip Select
Address Bus 0 to 13
Data Bus 0-15
Data Transfer
Acknowledgment
Output Drive Enable
CC
NAME
I/O
I/O These pins are the data bits of the microprocessor port.
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock
when data streams @ 2.048 Mb/s, a 8.192 MHz clock when data streams @ 4.096 Mb/s, a 16.384 MHz
When LOW, this pin is the frame measurement input. When HIGH, the HCLK (4.096 MHZ clock) is required
If this pin is unused, an external pull-up or pull-down must be provided.
Ground Rail.
+3.3 Volt Power Supply.
Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS
clock when data streams @ 8.192 Mb/s.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
Provides the clock to the JTAG test logic.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V70840 is in the normal functional mode.
This input (active LOW) puts the IDT72V70840 in its reset state that clears the device internal counters,
registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the RESET pin must be held LOW for a minimum of 100ns to reset the device.
When 1, enables the wide frame pulse (SFP) Frame Alignment interface. When 0, the device operates in
ST-BUS
This active LOW input works in conjunction with CS to enable the read and write operations.
This input controls the direction of the data bus lines during a microprocessor access.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70840.
These pins allow direct access to Connection Memory, Data Memory and internal control registers.
This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the connection memory.
for frame alignment in the wide frame pulse (WFP) mode. There is no internal pull-up or pull-down.
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
®
®
and GCI specifications.
/GCI mode.
3
DESCRIPTION
COMMERCIAL TEMPERATURE RANGE