IDT72V73260BB IDT, Integrated Device Technology Inc, IDT72V73260BB Datasheet - Page 12

• Manufacturer Part Number: IDT72V73260BB
• Description: IC DGTL SW 16384X16384 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V73260BB

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V73260BB

TABLE 10 — IDENTIFICATION REGISTER DEFINITIONS
TABLE 11 — SCAN REGISTER SIZES
JTAG SUPPORT
IEEE-1149.1. This standard specifies a design-for-testability technique called
Boundary-Scan test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
IDT72V73260. It consists of three input pins and one output pin.
on-chip clock and thus remains independent. The TCK permits shifting of test
data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not
driven from an external source.
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
of either the instruction register or data register are serially shifted out through
the TDO pin on the falling edge of each TCK pulse. When no data is shifted
through the boundary scan cells, the TDO driver is set to a high-impedance state.
NOTES:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
Revision Number (31:28)
IDT Device ID (27:12)
IDT JEDEC ID (11:1)
ID Register Indicator Bit (Bit 0)
The IDT72V73260 JTAG interface conforms to the Boundary-Scan standard
The Test Access Port (TAP) provides access to the test functions of the
•Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with any
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
•Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
•Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the contents
Instruction (IR)
Bypass (BYR)
Identification (IDR)
Boundary Scan (BSR)
the IDT website (www.idt.com), or by contacting your local IDT sales representative.
INSTRUCTION FIELD
REGISTER NAME
VALUE
0x436
0x33
0x0
BIT SIZE
1
Note(1)
32
4
1
12
Indicates the presence of an ID register
Reserved for version number
Defines IDT part number
Allows unique identification of device vendor as IDT
is not driven from an external source.
INSTRUCTION REGISTER
instructions. The IDT72V73260 JTAG interface contains a four-bit instruction
register. Instructions are serially loaded into the instruction register from the TDI
when the TAP Controller is in its shift-IR state. Subsequently, the instructions are
decoded to achieve two basic functions: to select the test data register that may
operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register
scanning. See Table 12 for Instruction decoding.
TEST DATA REGISTER
test data registers:
arranged to form a scan path around the boundary of the IDT72V73260 core
logic.
from TDI to TDO. The IDT72V73260 boundary scan register bits are shown
in Table 14. Bit 0 is the first bit clocked out. All three-state enable bits are active
HIGH.
ID CODE REGISTER
Number, Device ID, JEDEC ID, and ID Register Indicator Bit. See Table 10.
As specified in IEEE-1149.1, this instruction loads the IDR with the Revision
•Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC when it
In accordance with the IEEE-1149.1 standard, the IDT72V73260 uses public
As specified in IEEE-1149.1, the IDT72V73260 JTAG Interface contains two
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
•The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path
DESCRIPTION
INDUSTRIAL TEMPERATURE RANGE