AM85C30-10 AMD [Advanced Micro Devices], AM85C30-10 Datasheet - Page 24

• Manufacturer Part Number: AM85C30-10
• Description: Enhanced Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Interrupt Acknowledge Cycle Timing
NO TAG illustrates Interrupt Acknowledge cycle timing.
Between the time INTACK goes Low and the falling
edge of RD, the internal and external IEI/IEO daisy
chains settle. If there is an interrupt pending in the ESCC
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AMD
INTACK
D
7
–D
RD
0
A/B, D/C
A/B, D/C
INTACK
INTACK
D
D
7
7
–D
–D
WR
WR
CE
CE
0
0
Figure 12. Interrupt Acknowledge Cycle Timing
Figure 10. Read Cycle Timing
Figure 11. Write Cycle Timing
Am85C30
Address Valid
Address Valid
and IEI is High when RD falls, the Acknowledge cycle is
intended for the SCC. In this case, the ESCC may be
programmed to respond to RD Low by placing its inter-
rupt vector on D
rupt-Under-Service latch internally.
Data Valid
Data Valid
7
Vector
–D
0
; it then sets the appropriate Inter-
10216F-14
10216F-15
10216F-16