AM85C30-10 AMD [Advanced Micro Devices], AM85C30-10 Datasheet - Page 36

• Manufacturer Part Number: AM85C30-10
• Description: Enhanced Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Auto Flag Mode
On the NMOS Am8530H, if the transmitter is actively
mark idling and a frame of data is ready to be transmit-
ted, the Mark/Flag Idle bit must be set to 0 before data is
written to WR8, otherwise the opening flag will not be
sent properly. However, care must be exercised in doing
this because the mark idle pattern (eight 1 bits) is trans-
mitted 8 bits at a time, and all 8 bits must have trans-
ferred out of the Transmit Shift Register before a flag
may be loaded and sent. If data is written into the Trans-
mit Buffer (WR8) before the flag is loaded into the Trans-
mit Shift Register, the data character written to WR8 will
supersede flag transmission and the opening flag will
not be transmitted.
On the CMOS Am85C30, if bit D
the ESCC is programmed for SDLC operation, an option
is provided via bit D
quirement. If bit D
written to the Transmit Buffer while the transmitter is
mark idling, the Mark/Flag Idle bit in WR10 need not be
reset to 0 in order to have the opening flag sent because
the transmitter will automatically send it before com-
mencing to send data.
In addition, as long as bit D
are set to 1, the CRC transmit generator will be auto-
matically preset to the initial state programmed by bit D
of WR10 (so the Reset Tx CRC Generator command is
also not necessary), and the Tx Underrun/EOM latch
will be reset automatically on every new frame sent. This
ensures that an opening flag and proper CRC genera-
tion and transmission will always be sent without proc-
essor intervention under varying bus latency conditions.
Auto Transmit CRC Generator Preset
The NMOS Am8530H does not automatically preset the
CRC generator prior to frame transmission. This must
be done in software, usually during the initialization rou-
tine. This is accomplished by issuing the Reset Tx CRC
Generator Command via WR0. For proper results, this
command must be issued while the transmitter is en-
abled and idling and before any data are written to the
Transmit Buffer.
In addition, if CRC is to be used, the transmit CRC gen-
erator must be enabled by setting bit D
CRC is normally calculated on all characters between
opening and closing flags, so this bit should be set to 1 at
initialization and never changed.
On the CMOS Am85C30, setting bit D
cause the transmit CRC generator to be preset auto-
matically every time an opening flag is sent, so the Re-
set Tx CRC Generator Command is not necessary.
Auto Tx Underrun/EOM Latch Reset
On the ESCC, the transmission of the CRC check char-
acters is controlled by the Transmit CRC Enable bit in
36
AMD
0
of WR7 is set to 1 and a character is
0
of WR7 that eliminates this re-
0
of WR15 and bit D
0
of WR15 is set to 1 and
0
of WR15 to 1 will
0
of WR5 to 1.
1
of WR7
Am85C30
7
WR5 (D
However, if the Transmit Enable bit is set to 0 when a
transmit underrun (i.e., both the Transmit Buffer and
Transmit Shift Register become empty) occurs, the
CRC check characters will not be sent regardless of the
state of the Tx Underrun/EOM bit.
If the Transmit Enable bit is set to 1 when an underrun
occurs, then the state of the Tx Underrun/EOM bit and
the Abort/Flag on Underrun bit in WR10 (D
the action taken by the transmitter. The Abort/Flag on
Underrun bit may be set or reset by the processor,
whereas the Tx Underrun/EOM bit is set by the transmit-
ter and can only be reset by the processor via the Reset
Tx Underrun/EOM Command in WR0.
If the Tx Underrun/EOM bit is set to 1 when an underrun
occurs, the transmitter will close the frame by sending a
flag; however, if this bit is set to 0, the frame data will be
appended with either the accumulated CRC characters
followed by a flag or an abort pattern followed by a flag,
depending on the state of the Abort/Flag on Underrun bit
in the WR10 (D
sent, the transmitter will idle the transmission line as
specified by the Mark/Flag Idle bit D
Hence, if the CRC check characters are to be properly
appended to a frame, the Abort/Flag on Underrun bit
must be set to 0, and the Reset Tx Underrun/EOM Com-
mand must be issued after the first but before the last
character is written to the Transmit Buffer. This will en-
sure that either an abort or the CRC will be transmitted if
an underrun occurs. Normally, the Abort/Flag on Under-
run bit in WR10 should be set to 1 around the same time
that the Tx Underrun/EOM bit is reset so that an abort
will be sent if the transmitter accidentally underruns, and
then set to 0 near the end of the frame to allow the cor-
rect transmission of CRC.
On the Am85C30, if bit D
of having the Tx Underrun/EOM bit reset automatically
at the start of every frame is provided via bit D
This helps alleviate the software burden of having to re-
spond within one character time when high-speed data
are being sent.
SDLC/HDLC NRZI Transmitter Disabling
On the NMOS Am8530H, if NRZI encoding is being
used and the transmitter is disabled, the state of the TxD
pin will depend on the last bit sent. That is, the TxD pin
may either idle in a Low or High state as shown in
Figure 18.
On the CMOS Am85C30, an option is provided that al-
lows setting the TxD pin High when operating in SDLC
mode with NRZI encoding enabled. If bit D
set to 1, then bit D
pin High. Note that the operation of this bit is independ-
ent of the Tx Enable bit in WR5. The Tx Enable bit in
WR5 is used to disable and enable the transmitter,
0
) and the Tx Underrun/EOM bit in RR0 (D
2
). In either case, after the closing flag is
3
of WR7 can be used to set the TxD
0
of WR15 is set to 1, the option
3
in WR10.
0
2
) determine
of WR15 is
1
of WR7 .
6
).