K4T51043QC-ZCCC SAMSUNG [Samsung semiconductor], K4T51043QC-ZCCC Datasheet
K4T51043QC-ZCCC
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K4T51043QC-ZCCC Summary of contents
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... C-die DDR2 SDRAM 512Mb C-die DDR2 SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... C-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout & Mechanical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page DDR2 SDRAM Rev. 1.4 Aug. 2005 ...
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... The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16). Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of oper- ation. 85°C, CASE Page DDR2 SDRAM DDR2-400 3-3-3 K4T51043QC-ZC(L)CC K4T51083QC-ZC(L)CC K4T51163QC-ZC(L)CC DDR2-533 DDR2-400 4-4-4 3-3 ...
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... C-die DDR2 SDRAM 2. Package Pinout/Mechanical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package Ball Locations (x4 VDD NC VSS A VSSQ NC DQS VSSQ DM B VDDQ VDDQ VDDQ DQ1 C VSSQ NC DQ3 DQ2 D VDDL VREF VSSDL VSS E CKE WE F RAS ...
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... C-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package Ball Locations (x8 NU/ VDD VSSQ VSS A RDQS DM/ DQ6 VSSQ DQS B RDQS VDDQ DQ1 VDDQ VDDQ C VSSQ DQ3 DQ2 DQ4 D VDDL VREF VSS VSSDL E CKE WE RAS F BA0 BA1 NC G CAS ...
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... C-die DDR2 SDRAM x16 package pinout (Top View) : 84ball FBGA Package 1 VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Note : 1. VDDL and VSSDL are power and ground for the DLL case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used. ...
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... C-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- 0.45± ∅ ∅0 #A1 10.00 ± 0.10 6.40 0.80 1. 3.20 (5.00) (0.90) (1.80) 0.05 10.00 ± 0.10 Page DDR2 SDRAM # A1 INDEX MARK 0.35± 0.05 MAX.1.20 Rev. 1.4 Aug. 2005 ...
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... C-die DDR2 SDRAM FBGA Package Dimension(x16 84- 0.45± ∅ ∅0 #A1 11.00 ± 0.10 6.40 0.80 1. 3.20 (5.50) (0.90) 0.05 (1.80) 11.00 ± 0.10 Page DDR2 SDRAM # A1 INDEX MARK 0.35± 0.05 MAX.1.20 Rev. 1.4 Aug. 2005 ...
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... Input Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration ODT is applied to each ODT Input DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal ...
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... C-die DDR2 SDRAM 2.3 512Mb Addressing Configuration # of Banks Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Banks Bank Address Auto precharge Row Address Column Address 1Gb Configuration ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. ...
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... Symbol TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate ...
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... C-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V AC differential input voltage ID(AC differential cross point voltage IX(AC) Notes (AC) specifies the input differential voltage |V ID and V is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal ...
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... The absolute value of the slew rate as measured from equal to or greater than the slew rate as measured from AC to AC. This is guaran- teed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load : 7 ...
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... C-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; ...
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... C-die DDR2 SDRAM Notes : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11 ...
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... IDD0 tbd IDD1 tbd IDD2P tbd IDD2Q tbd IDD2N tbd IDD3P-F tbd IDD3P-S tbd IDD3N tbd IDD4W tbd IDD4R tbd IDD5 tbd IDD6 tbd IDD7 tbd 128Mx4(K4T51043QC) 667@CL=5 533@CL=4 CE6 LE6 CD5 100 ...
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... C-die DDR2 SDRAM DDR2 SDRAM IDD Spec Table(2) Symbol 800@CL=5 CE7 LE7 IDD0 tbd IDD1 tbd IDD2P tbd IDD2Q tbd IDD2N tbd IDD3P-F tbd IDD3P-S tbd IDD3N tbd IDD4W tbd IDD4R tbd IDD5 tbd IDD6 tbd IDD7 tbd 32Mx16(K4T51163QC) 667@CL=5 ...
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... C-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS CDIO Electrical Characteristics & AC Timing for DDR2-800/667/533/400 (0 ° ...
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... C-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & ...
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... C-die DDR2 SDRAM Parameter Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (slow exit, lower power) CKE minimum pulse width (high and low pulse width) ...
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... The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig- nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure. ...
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... DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent ...
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... C-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...
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... C-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns ∆tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/Ad- dress Slew 0.8 -25 rate (V/ns) 0.7 -43 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Command/Ad- 0.8 -13 dress Slew rate ...
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... C-die DDR2 SDRAM For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS 19 ...
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... C-die DDR2 SDRAM tHZ tRPST end point tHZ,tRPST end point = 2*T1-T2 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V tial data strobe crosspoint for a rising signal, and from the input signal crossing at the V nal applied to the device under test ...
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... C-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V device under test. 32. Input waveform timing is referenced from the input signal crossing at the V device under test 33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency. 34. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the VIH(ac) level to the sin- gle-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single- ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test ...
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... C-die DDR2 SDRAM Revision History Version 1.0 (Feb. 2005) - Initial Release Version 1.1 (Mar. 2005) - Added Low power current values for 533&400 speed - Changed IDD3N/2Q normal current values for x16 org. Version 1.2 (May 2005) - Corrected typo Version 1.3 (Jul. 2005) - Revised the Odering Information Version 1 ...