K4T1G044QM-ZCCC SAMSUNG [Samsung semiconductor], K4T1G044QM-ZCCC Datasheet - Page 15

• Manufacturer Part Number: K4T1G044QM-ZCCC
• Description: 1Gb M-die DDR2 SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

1Gb M-die DDR2 SDRAM
IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Proposed Conditions
Operating one bank active-precharge current;
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RC = t RC (IDD), t RAS = t RAS-
min(IDD), t RCD = t RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address busin-
puts are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current;
All banks idle; t CK = t CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby current;
All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare
STABLE; Data bus inputs are FLOATING
Precharge standby current;
All banks idle; t CK = t CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; t CK = t CK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
All banks open; t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; t CK = t CK(IDD), t RAS =
t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; t CK =
t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD); CKE is HIGH, CS\ is HIGH between valid com-
mands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Burst auto refresh current;
t CK = t CK(IDD); Refresh command at every t RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = t RCD(IDD)-1* t CK(IDD); t CK =
t CK(IDD), t RC = t RC(IDD), t RRD = t RRD(IDD), t RCD = 1* t CK(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; Refer to the following page for detailed timing conditions
t CK = t CK(IDD), t RC = t RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid
Page 15 of 29
Fast PDN Exit MRS(12) =
0mA
Slow PDN Exit MRS(12) =
1mA
Normal
Low Power
Rev.1.1 Jan. 2005
DDR2 SDRAM
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes