K4S561633F-E SAMSUNG [Samsung semiconductor], K4S561633F-E Datasheet

K4S561633F-E

Manufacturer Part Number

K4S561633F-E

Description

4M x 16Bit x 4 Banks Mobile SDRAM in 54BOC

Manufacturer

SAMSUNG [Samsung semiconductor]

Datasheet

1.K4S561633F-E.pdf (12 pages)

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K4S561633F - X(Z)E/N/G/C/L/F

4M x 16Bit x 4 Banks Mobile SDRAM in 54BOC

FEATURES

• 3.0V & 3.3V power supply.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system

• Burst read single-bit write operation.

• Special Function Support.

• DQM for masking.

• Auto refresh.

• 64ms refresh period (8K cycle).

• Commercial Temperature Operation (-25°C ~ 70°C).

• Extended Temperature Operation (-25°C ~ 85°C).

• 54Balls BOC with 0.8mm ball pitch

ORDERING INFORMATION

- X(Z)E/N/G : Normal / Low / Low Power, Extended Temperature(-25°C ~ 85°C)

- X(Z)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)

NOTES :

1. In case of 40MHz Frequency, CL1 can be supported.

2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.

Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific

purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

clock

( -X : Leaded, -Z : Lead Free).

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

K4S561633F-X(Z)E/N/G/C/L/F1H

K4S561633F-X(Z)E/N/G/C/L/F75

K4S561633F-X(Z)E/N/G/C/L/F1L

Part No.

105MHz(CL=3)

133MHz(CL=3)

105MHz(CL=2)

Max Freq.

GENERAL DESCRIPTION

rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits,

fabricated with SAMSUNG's high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock and I/O transactions are possible on every

clock cycle. Range of operating frequencies, programmable

burst length and programmable latencies allow the same device

to be useful for a variety of high bandwidth, high performance

memory system applications.

The K4S561633F is 268,435,456 bits synchronous high data

Interface

LVCMOS

Mobile-SDRAM

Leaded (Lead Free)

Package

54 BOC

February 2004

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