SSD1815BT ETC1 [List of Unclassifed Manufacturers], SSD1815BT Datasheet - Page 8

• Manufacturer Part Number: SSD1815BT
• Description: LCD Segment / Common Driver with Controller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

V
are referenced to V
bias divider, by turning on the output op-amp buffers option in
the Set Power Control Register command.
V
supplied externally or generated by turning on the internal reg-
ulator option in the Set Power Control Register command.
V
erating V
to generate the LCD driving level, V
and R
V
M/S
pin is pulled high, master mode is selected, which CL, M,
MSTAT and DOF signals will be output for slave devices.
CL, M, DOF are required to be input from master device and
MSTAT is high impedance.
CLS
pulled high, internal clock is enabled.
external clock source must be input to CL pin for normal opera-
tion.
C68/80
pin is pulled high, 6800 series interface is selected and when the
pin is pulled low, 8080 series interface is selected.
this pin is ignored, but must be connected to a known logic (ei-
ther high or low).
P/S
pin is pulled high, parallel interface mode is selected. When it is
pulled low, serial interface will be selected.
(WR), E/(RD) is recommended to be connected to Vss.
mode.
SOLOMON
L6
L2
L6
F
, respectively (see application circuit diagrams).
, V
These are the LCD driving voltage levels. All these levels
They can be supplied externally or generated by the internal
The potential relation of these pins are given as:
and with bias factor, a,
This pin is the most negative LCD driving voltage. It can be
This pin is the input of the built-in voltage regulator for gen-
When external resistor network is selected (IRS pulled low)
This pin is the master/slave mode selection input. When this
When this pin is pulled low, slave mode is selected, which
This pin is the internal clock enable pin. When this pin is
The internal clock will be disabled when it is pulled low, an
This pin is MCU parallel interface selection input. When the
If Serial Interface is selected (P/S pulled low), the setting of
This pin is serial/parallel interface selection input. When this
Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/W/
Note2: Read Back operation is only available in parallel
2
, should be connected between V
L3
L6
, V
.
L4
V
V
V
V
V
DD
L2
L3
L4
L5
and V
- V
- V
- V
- V
> V
DD
DD
DD
DD
DD
L 2
.
L5
= 1/a * (V
= 2/a * (V
= (a-2)/a * (V
= (a-1)/a * (V
> V
L3
> V
L6
L6
L4
L 6
- V
- V
> V
L6
L6
, two external resistors, R
DD
DD
- V
- V
L5
DD
)
)
DD
DD
> V
and V
)
)
L 6
F
, and V
F
and
1
HPM
The function of this pin is only enabled for High Power model
which required special ordering.
LCD driving characteristics are the same no matter this pin is
pulled High or Low.
this pin floating is prohibited.
IRS
for the voltage regulator. When this pin is pulled high, the internal
feedback resistors of the internal regulator for generating V
be enabled.
be connected to V
application circuit diagrams).
ROW0 - ROW63
panel. See Table 3 on page 10 for the COM signal mapping in
SSD1815B.
SEG0 - SEG131
output voltage level of these pins is V
standby mode.
ICONS
pins output exactly the same signal. The reason for duplicating
the pin is to enhance the flexibility of the LCD layout.
NC
nected to these pins, nor they are connected together. These
pins should be left open individually.
This pin is the control input of High Power Current Mode.
For normal models, High Power Mode is disabled and the
Note: This pin must be pulled to either High or Low. Leaving
This is the input pin to enable the internal resistors network
When it is pulled low, external resistors, R
These pins provide the Common driving signals to the LCD
These pins provide the LCD segment driving signals. The
There are two ICONS pins (pin12 and 136) on the chip. Both
These are the No Connection pins. Nothing should be con-
DD
and V
F
, and V
07/2002
Rev1.6
F
and V
DD
during sleep mode and
L6
, respectively (see
1
and R
SSD1815B
2
, should
L6
will
9