GS820322T-138 ETC1 [List of Unclassifed Manufacturers], GS820322T-138 Datasheet

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GS820322T-138

Manufacturer Part Number
GS820322T-138
Description
64K x 32 2M Synchronous Burst SRAM
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
TQFP, QFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP or QFP package
Functional Description
Applications
The GS82032 is a 2,097,152-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.04 2/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Through
Pipeline
3-1-1-1
2-1-1-1
operation
Flow
tCycle
tCycle
t
I
t
I
KQ
DD
KQ
DD
-150 -138 -133 -117 -100
10.5
270
170
6.6
3.8
9
7.25
245
120
9.7
15
4
240
120
2M Synchronous Burst SRAM
7.5
15
10
4
1
, E
210
120
8.5
4.5
15
11
2
, E
3
180
120
), address burst
10
15
12
5
12.5
150
-66
20
18
95
6
64K x 32
1/23
Unit
mA
mA
ns
ns
ns
ns
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin/bump (Pin 14 in the TQFP, Bump
1F in the FP-BGA). Holding the FT mode pin/bump low,
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered
Data Output Register.
SCD Pipelined Reads
The GS82032 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS82032 operates on a 3.3 V power supply and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output
power (V
internal circuit.
DDQ
) pins are used to decouple output noise from the
GS82032T/Q-150/138/133/117/100/66
© 2000, Giga Semiconductor, Inc.
3.3 V and 2.5 V I/O
150 MHz–66 MHz
Preliminary
9 ns–18 ns
3.3 V V
DD

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GS820322T-138 Summary of contents

Page 1

... The GS82032 is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers ...

Page 2

GS82032 100-Pin TQFP and QFP Pinout 100 DDQ ...

Page 3

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78 ...

Page 4

GS82032 Block Diagram Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Rev: 1.04 2/2001 Specifications ...

Page 5

Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected ...

Page 6

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 7

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E inputs, and that ADSP ...

Page 8

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 9

Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage on V Pins Voltage in V Pins DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V ...

Page 10

... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87. 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1. ...

Page 11

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 12

Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032T/Q-150/138/133/117/100/66 12/23 Preliminary © 2000, Giga Semiconductor, Inc. ...

Page 13

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Clock ...

Page 14

Write Cycle Timing Single Write ADSP ADSC ADV –An 0 WR1 – Hi-Z DQ –DQ A ...

Page 15

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV –An RD1 – tOLZ DQ ...

Page 16

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV tS tH A0–An RD1 – tOE G tKQ Hi-Z DQ ...

Page 17

Pipelined SCD Read Cycle Timing Single Read ADSP ADSC ADV RD1 – Hi-Z DQ – Rev: ...

Page 18

Pipelined SCD Read-Write Cycle Timing Single Read ADSP ADSC ADV –An 0 RD1 – Hi-Z DQa–DQd ...

Page 19

... Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles, and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention ...

Page 20

GS 82032 Output Driver Characteristics 60 Pull Down Drivers -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 3. Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see ...

Page 21

TQFP and QFP Package Drawing Symbol Description A1 A2 Body Thickness b c Lead Thickness D Terminal Dimension D1 Package Body E Terminal Dimension E1 Package Body Notes: 1. All dimensions ...

Page 22

... Ordering Information 1 Org Part Number 64K x 32 GS82032T-150 64K x 32 GS820322T-138 64K x 32 GS82032T-133 64K x 32 GS82032T-4 64K x 32 GS82032T-5 64K x 32 GS82032T-6 64K x 32 GS82032T-150I 64K x 32 GS82032T-138I 64K x 32 GS82032T-133I 64K x 32 GS82032T-4I 64K x 32 GS82032T-5I 64K x 32 GS82032T-6I ...

Page 23

... Rev: 1.04 2/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Revisions • This was the first release of 2 Meg Burst Datasheets in the Format new format. They included information for the Fine Pitch BGA package. • Took out the Fine Pitch BGA information. ...

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