GS82032A ETC1 [List of Unclassifed Manufacturers], GS82032A Datasheet - Page 7

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GS82032A

Manufacturer Part Number
GS82032A
Description
2M Synchronous Burst SRAM
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet

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Notes:
1.
2.
3.
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Simplified State Diagram
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
The upper portion of the diagram assumes active use of only the Enable (E
and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
CW
7/23
W
CR
R
CR
R
Deselect
X
1,
E
2,
E
3
) and Write (B
R
GS820E32T/Q-150/138/133/117/100/66
CR
First Read
Burst Read
R
R
A
, B
B
, B
CR
C
X
, B
X
© 1999, Giga Semiconductor, Inc.
D
, BW and GW) control inputs
D

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