GS8644Z18 ETC [List of Unclassifed Manufacturers], GS8644Z18 Datasheet

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GS8644Z18

Manufacturer Part Number
GS8644Z18
Description
72Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GS8644Z18B-150
Manufacturer:
GSI
Quantity:
20 000
119-, 165-, & 209-Pin BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 9Mb, 18Mb, and 36Mb
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-bump BGA package
Functional Description
The GS8644Z18/36/72 is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
devices
Through
Pipeline
3-1-1-1
2-1-1-1
Flow
72Mb Pipelined and Flow Through
t
Synchronous NBT SRAM
KQ (x18/x36)
Curr
Curr
Curr
Curr
Curr
Curr
t
KQ (x72)
tCycle
tCycle
t
KQ
(x18)
(x36)
(x72)
(x18)
(x36)
(x72)
Parameter Synopsis
1/39
-250 -225 -200 -166 -150 -133 Unit
385
450
540
265
290
345
2.5
3.0
4.0
6.5
6.5
360
415
505
265
290
345
2.7
3.0
4.4
6.5
6.5
GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C)
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8644Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8644Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
335
385
460
265
290
345
3.0
3.0
5.0
6.5
6.5
305
345
405
255
280
335
3.5
3.5
6.0
7.0
7.0
295
325
385
240
265
315
3.8
3.8
6.7
7.5
7.5
265
295
345
225
245
300
4.0
4.0
7.5
8.5
8.5
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns
ns
Product Preview
© 2003, GSI Technology
250 MHz–133MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS8644Z18

GS8644Z18 Summary of contents

Page 1

... This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8644Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising edge triggered output register ...

Page 2

... TMS D D Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72( ADV ...

Page 3

... CKE Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Description Address field LSBs and Address Counter Preset Inputs. Address Inputs Data Input and Output pins Byte Write Enable for I/Os ...

Page 4

... DDQ Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Description Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground ...

Page 5

... DQD V M DDQ N DQD P DQD DDQ Bump BGA— Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72( ADV ...

Page 6

... GS8644Z18B Pad Out—119-Bump BGA—Top View (Package DDQ DQB DDQ DQB V J DDQ DQB V M DDQ N DQB DDQ Bump BGA— Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 7

... GS8644Z18/36 119-Bump BGA Pin Description Symbol Type I — CKE ADV LBO TMS I TDI O TDO TCK ...

Page 8

... NC V DDQ LBO Bump BGA— Body—1.0 mm Bump Pitch Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72( CKE ADV ...

Page 9

... NC V DDQ LBO Bump BGA— Body—1.0 mm Bump Pitch Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72( CKE ADV ...

Page 10

... GS8644Z18/36E 165-Bump BGA Pin Description Symbol Type I — CKE ADV LBO I TMS I I TDI O TDO I TCK MCH — ...

Page 11

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72( ...

Page 12

... This device contains circuitry that ensures all outputs are in High Z during power-up 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) External L ...

Page 13

... Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72( Deselect ...

Page 14

... Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Pipeline Mode Data I/O State Diagram Intermediate R Intermediate D Intermediate W R ...

Page 15

... Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Flow Through Mode Data I/O State Diagram High ...

Page 16

... There are pull-up devices onthe ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Pin Name State L ...

Page 17

... GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device, the pin will need to be pulled low for correct operation. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Interleaved Burst Sequence 10 11 ...

Page 18

... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Description Voltage on V Pins DD ...

Page 19

... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Symbol Min. Typ. V 2.0 — ...

Page 20

... Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Overshoot Measurement and Timing 50% ...

Page 21

... ZZ Input Current FT and ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Symbol Test Conditions ≥ ...

Page 22

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) 22/39 Product Preview © 2003, GSI Technology ...

Page 23

... asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) -250 -225 Min ...

Page 24

... A B A0–An DQa–DQd G *Note High(False Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Pipeline Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH ...

Page 25

... TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Flow Through Mode Timing (NBT) Write B+1 Read C ...

Page 26

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Description 26/39 Product Preview ...

Page 27

... Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) JTAG TAP Block Diagram (2-die module) · ...

Page 28

... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Not Used Configuration 0 ...

Page 29

... I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) JTAG Tap Controller State Diagram 1 1 ...

Page 30

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) 30/39 Product Preview © 2003, GSI Technology ...

Page 31

... Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Conditions V – V/ns ...

Page 32

... The TDO output driver is served by the –4 mA OHJ OLJ –100 uA OHJC +100 uA OHJC Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Symbol V IHJ3 V ILJ3 V IHJ2 V ILJ2 I INHJ I INLJ I OLJ V OHJ V ...

Page 33

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) JTAG Port Timing Diagram tTKC tTKC ...

Page 34

... Symbol Min Typ A — — A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 Rev 1.0 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) 209 BGA Package Drawing (Package ∅b e Max Units Symbol 22.1 mm ...

Page 35

... SEATING PLANE C Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) BOTTOM VIEW Ø0. Ø0. Ø0.44~0.64(165x 1.0 10.0 15±0. ...

Page 36

... SEATING PLANE C Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0. ...

Page 37

... GS8644Z72C-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644Z18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 38

... GS8644Z72C-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644Z18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 39

... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644Z18(B/E)/GS8644Z36(B/E)/GS8644Z72(C) Page;Revisions;Reason • Creation of new datasheet • Updated Operating Currents table Content • Updated FT AC Characteristics for tKQ • Updated FT tKQ and PL tS/tH and FT current numbers for 250 and 225 MHz (match 200 MHz) • ...

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