AM53CF94JCW AMD [Advanced Micro Devices], AM53CF94JCW Datasheet - Page 36

• Manufacturer Part Number: AM53CF94JCW
• Description: Enhanced SCSI-2 Controller (ESC)
• Manufacturer: AMD [Advanced Micro Devices]

Data Alignment Register (0FH) Write
The Data Alignment Register (DALREG) is used if the
first byte of a 16-bit DMA transfer from the SCSI bus to
the host processor is misaligned. Prior to issuing an in-
formation transfer command, the host processor must
set the Data Alignment Enable (DAE) bit in Control Reg-
ister Two (CNTLREG2).
This register may be loaded immediately following the
phase change to Synchronous Data In. This byte will
become the LSB of the first word transmitted from the
FIFO to the DMA controller. The MSB will be comprised
of the first byte received over the SCSI bus. Together,
these bytes constitute the first 16-bit word transferred to
memory.
DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0
36
Data Alignment Register
DALREG
DA7
7
0
AMD
DA6
6
0
DA5
5
0
DA4
4
0
DA3
3
0
DA2
2
0
Address: OF
DA1
1
0
Type: Write
17348B-34
Am53CF94/Am53CF96
P R E L I M I N A R Y
DA0
0
0
H
Part-Unique ID Register (0EH) Read Only
This register extends the transfer counter from 16 to 24
bits and is only enabled when the ENF bit is set (bit 6,
Control Register Two). The descriptions accompanying
the Start Transfer Count Registers and the Current
Count Registers should be referenced for more informa-
tion regarding the transfer counter.
This register is also used to store the part-unique ID
code for the Am53CF94/96. This information may be ac-
cessed when all of the following are true:
1) A value has not been loaded into this register
2) A DMA NOP command has been issued (code 80h)
3) Bit 6 in Control Register Two is set (ENF bit)
4) A power up or chip reset has taken place
When the above conditions are satisfied, the following
bit descriptions apply:
Am53CF94, 3 V
Am53CF94, 5 V
12
12
ID