R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 119

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
3.2.2
3.2.3
R e v 1 . 0 1
Operations and Cautions for Clock Stopped State
BRDY Interrupt
VBINT, RESM, and BCHG interrupt factors will be generated even when the clock is stopped (including low-power
sleep state) and, when enabled in the interrupt enable register, the interrupt from the INT_N pin will be asserted.
Clear the interrupt factors after executing the clock supply start process.
When a BCHG interrupt is generated due to the Peripheral Device attach/detach while the clock is stopped, either the
ATCH interrupt or the DTCH interrupt will be generated after the clock is re-started. Therefore, the attach/detach
process may be executed due to the ATCH interrupt or the DTCH interrupt rather than the BCHG interrupt, depending
on the determined order of interrupt factors and software process speed.
The BRDY interrupt is generated when either the Host or Peripheral function has been selected. Interrupt generation
conditions are as shown in listed in 2.11.21. Figure 3.7 provides the BRDY interrupt generation timing diagram.
When a zero-length packet is received, the corresponding bit of the BRDYSTS register goes to “1” but the data of the
corresponding packet cannot be read. Clear the buffer (“BCLR=1”) after clearing the BRDYSTS register.
In addition, interrupts can be generated in transfer units in PIPE1 to PIPE9 when using DMA transfers in the read
direction by setting the PIPECFG register BFRE bit to “1”.
O c t 1 7 , 2 0 0 8
*1) ACK Handshake is not existing in iso chro no us transfers
*2) Conditions fo r FIFO buffer to be read-e nabled:
*3) Transfer co mplete co nditio ns:
(3) Example of packet send (single buffer setting)
(1) Example of zero-length packet receive or data packet receive when BFRE=0 (single buffer setting)
(2) Data packet receive when BFRE=1 (single buffer setting)
BRDY Interrupt
BRDY Interrupt
PIPEBRDY bit)
BRDY Interrupt
PIPEBRDY bit)
PIPEBRDY bit)
corresponding
corresponding
corresponding
One o f the following read events is generated when no unread data remains in the CPU buffer memory
(1) 1 packet receive d in no n-continuo us transfer mo de, or
(2) one of the following receive e vents i n the co ntinuo us transfer mode
W hen one of the followi ng receive events occurs
(1) receive short packet (i ncl. zero-leng th), or
(2) receive packets equal to number o f packets in transaction counter
(Change in
(Change in
(Change in
Packet sent by Host
FIFO buffer
FIFO buffer
FIFO buffer
(a) receive short packet (incl. zero-le ngth)
(b) buffer full o ccurs
(c) re ceive packets equa l to number of packets in transactio n co unter
USB Bus
USB Bus
USB Bus
status
status
status
Figure 3.7 BRDY Interrupt Generation Timing Diagram
p a g e 1 1 9 o f 1 8 3
Receive-enabled state
Receive-enabled state
Token Packet
Token Packet
Token Packet
Send-enabled state
Data Packet (Maximum size)
Data Packet (Maximum size)
Zero-Length Packet /
Zero-Length Packet /
Short Data Packet /
Short Data Packet /
Data Packet
Packet sent by Peripheral
Buffer m emory is read enabled
ACK Handshake
ACK Handshake
ACK Handshake
Buffer memory is read enabled
and BDRY interrupt is generated
and BDRY interrupt is generated
Buffer memory is read enabled
*1)
*1)
*1)
Read-enabled state
Read enabled state
Write-enabled state
*2
Transfer is completed
and BRDY interrupt is
*2
generated
*3