R8A66597BG RENESAS [Renesas Technology Corp], R8A66597BG Datasheet - Page 82

• Manufacturer Part Number: R8A66597BG
• Description: ASSP (USB2.0 2 Port Host/1 Port Peripheral Controller)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66597FP/DFP/BG
2.15.17 Control transfer end enabled (CCPL)
2.15.18 Response PID bit (PID)
2.15.18.1 When the Host Controller function is selected
2.15.18.2 When the Peripheral Controller function is selected
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When the Peripheral Controller function is selected, if the corresponding PID bit is "BUF" and the software writes "1" to
this bit, the controller completes the control transfer stage. In other words, it transmits an ACK handshake for the OUT
transaction from the USB Host during a Control Read Transfer, and transmits a zero-length packet for an IN
transaction from the USB Host during a Control Write and No Data Control Transfer. However, irrespective of the setup
value of this bit, the controller responds automatically from the Setup stage until the status stage is complete when a
SET_ADDRESS request is detected.
When a new Setup packet is received, the controller modifies this bit from "1" to "0".
When "VALID=1", the software cannot write "1" to this bit.
When the Host Controller function is selected, write "0" to this bit.
For this bit, while executing data stage or status stage of control transfer, use the software to modify this bit from
"NAK" to "BUF".
(1) When the software has written "BUF" to this bit and the controller receives the data exceeding the maximum
packet size, the controller sets "PID=STALL(11)".
(2) When a reception error such as a CRC error has been detected three times continuously, the controller sets
"PID=NAK".
(3) When a STALL handshake is received, the controller sets "PID=STALL(11)".
(1) When the controller receives the Setup packet, the controller modifies this bit to "NAK" ("00"). Here, the controller
sets "VALID=1" and the software cannot modify this bit until it writes "VALID=0".
Use the procedure below to modify this bit from "NAK" to "BUF":
(1) When setting transmission direction
(2) When setting reception direction
The controller changes the value of this bit in any of the following cases:
After an S-Split execution of a Split transaction in the pipe (when the controller sets CSSTS="1"), the controller
executes the transaction until the C-Split ends, even if the software has modified this bit to "NAK". The controller sets
"PID=NAK" when the C-Split ends.
The controller modifies the bit value in the following cases:
(2) When the software writes "BUF" to this bit and the controller receives the data exceeding the maximum packet
size, the controller sets "PID=STALL(11)".
(3) When the controller detects a control transfer sequence error, it sets "PID=STALL(1x)".
(4) When the controller detects a USB bus reset, it sets "PID=NAK".
During a SET_ADDRESS request process (auto process), the controller does not refer to the setup value of this bit.
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When "UACT=1" and "PID=NAK", complete the write of transmission data in the FIFO buffer and then write
"PID=BUF". Thereafter, the controller executes an OUT transaction (or PING transaction).
When "UACT=1" and "PID=NAK", check to see that the FIFO buffer is empty (change the status to empty) and
write "PID=BUF". Thereafter, the controller executes an IN transaction.
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