X25330V14I-2.5 Xicor, X25330V14I-2.5 Datasheet

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X25330V14I-2.5

Manufacturer Part Number
X25330V14I-2.5
Description
Manufacturer
Xicor
Datasheet
FUNCTIONAL DIAGRAM
7048–1.0 6/18/97 T0/C0/D0 SH
Direct Write
FEATURES
32K
Xicor, Inc. 1994 - 1997 Patents Pending
5MHz Clock Rate
Low Power CMOS
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
4K X 8 Bits
Block Lock™ Protection
Programmable Hardware Write Protection
Built-in Inadvertent Write Protection
Self-Timed Write Cycle
High Reliability
Packages
<5mA Active Current
<1 A Standby Current
32 Byte Page Mode
Protect 1/4, 1/2 or all of E
In-Circuit Programmable ROM Mode
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
5ms Write Cycle Time (Typical)
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
8-Lead SOIC
14-Lead TSSOP
and Block Lock
HOLD
SCK
SO
CS
WP
SI
5MHz SPI Serial E
Protection is a trademark of Xicor, Inc.
COMMAND
REGISTER
CONTROL
CONTROL
DECODE
ST ATUS
TIMING
WRITE
LOGIC
LOGIC
AND
AND
2
PROM Array
PROTECT
WRITE
LOGIC
2
PROM with Block Lock
X25330
1
DESCRIPTION
The X25330 is a CMOS 32K-bit serial E
nally organized as 4K x 8. The X25330 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25330 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25330 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25330 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25330 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
64
32
32
32
TM
DATA REGISTER
Y DECODE
64 X 256
4K BYTE
32 X 256
32 X 256
Protection
ARRAY
Characteristics subject to change without notice
8
7037 FRM F01
4K x 8 Bit
2
PROM, inter-
TM

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