W39L040A70B WINBOND [Winbond], W39L040A70B Datasheet
W39L040A70B
Related parts for W39L040A70B
W39L040A70B Summary of contents
Page 1
... DQ7: #Data Polling...........................................................................................................8 6.4.2 DQ6: Toggle Bit................................................................................................................9 6.5 Table of Operating Modes .............................................................................................. 9 6.5.1 Device Bus Operations.....................................................................................................9 6.5.2 Auto-select Codes (High Voltage Method) .......................................................................9 6.5.3 Sector Address Table .....................................................................................................10 6.5.4 Command Definitions .....................................................................................................10 6.6 Embedded Programming Algorithm ............................................................................. 11 6.7 Embedded Erase Algorithm.......................................................................................... 12 W39L040A Data Sheet 512K × 8 CMOS FLASH MEMORY Publication Release Date:April 14, 2005 - 1 - Revision A3 ...
Page 2
Embedded #Data Polling Algorithm.............................................................................. 13 6.9 Embedded Toggle Bit Algorithm ................................................................................... 13 7. ELECTRICAL CHARACTERISTICS......................................................................................... 14 7.1 Absolute Maximum Ratings .......................................................................................... 14 7.2 DC Operating Characteristics....................................................................................... 14 7.3 Pin Capacitance............................................................................................................ 14 7.4 AC Characteristics ........................................................................................................ 15 7.4.1 AC Test ...
Page 3
... GENERAL DESCRIPTION The W39L040A is a 4Mbit, 3V/3.3V CMOS flash memory organized as 512K × 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 3 ...
Page 4
PIN CONFIGURATIONS # 32L ...
Page 5
FUNCTIONAL DESCRIPTION 6.1 Device Bus Operation 6.1.1 Read Mode The read operation of the W39L040A is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is ...
Page 6
Byte 0 ( represents the manufacturer′s code (Winbond = DAH) and byte 1 ( device identifier code (W39L040A = D6hex). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as ...
Page 7
... Auto-select Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising high voltage. ...
Page 8
The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data ...
Page 9
DQ6: Toggle Bit The W39L040A also features the "Toggle Bit" method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to ...
Page 10
Sector Address Table SECTOR A18 SA0 0 SA1 0 SA2 0 SA3 0 SA4 1 SA5 1 SA6 1 SA7 1 Note: All sectors are 64K bytes in size. 6.5.4 Command Definitions COMMAND NO. OF 1ST CYCLE 2ND CYCLE ...
Page 11
Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data Publication Release Date: April 14, 2005 ...
Page 12
Embedded Erase Algorithm Write Erase Command Sequence Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H Start (see below) #Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H ...
Page 13
Embedded #Data Polling Algorithm 6.9 Embedded Toggle Bit Algorithm Start VA = Byte address for programming Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data ? Yes Pass Start Read Byte (DQ0 - DQ7) Address = ...
Page 14
ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER Operating Temperature Storage Temperature Power Supply Voltage Voltage on Any Pin to Ground Potential except A9 Voltage on A9, #OE Pin to Ground Potential Note: Exposure to conditions beyond ...
Page 15
AC Characteristics 7.4.1 AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 7.4.2 AC Test Load and Waveform (Including Jig and Scope 3.0V <5 nS 1.5V/1.5V 1 TTL Gate C = ...
Page 16
AC Characteristics, continued 7.4.3 Read Cycle Timing Parameters (V = 3.0 ~ 3.6V for 2.7 ~ 3.6V for 90 nS PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output ...
Page 17
AC Characteristics, continued 7.4.5 Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation 7.4.6 #Data Polling and Toggle Bit Timing Parameters PARAMETER #OE to #Data Polling Output Delay #CE to #Data Polling Output Delay #OE to Toggle Bit ...
Page 18
TIMING WAVEFORMS 8.1 Read Cycle Timing Diagram Address A18-0 #CE # #WE High-Z DQ7-0 8.2 #WE Controlled Command Write Cycle Timing Diagram Address A18-0 #CE #OE #WE DQ7 OLZ T ...
Page 19
Timing Waveforms, continued 8.3 #CE Controlled Command Write Cycle Timing Diagram Address A18-0 #CE #OE #WE DQ7-0 8.4 Chip Erase Timing Diagram Address A18-0 5555 DQ7-0 #CE #OE T #WE SB0 OES High Z ...
Page 20
Timing Waveforms, continued 8.5 Sector Erase Timing Diagram 5555 Address A18-0 DQ7-0 AA #CE # #WE SB0 SA = Sector Address 8.6 #Data Polling Timing Diagram Address A18-0 #WE #CE #OE DQ7 Six-byte commands for 3.3V-only Sector Erase ...
Page 21
Timing Waveforms, continued 8.7 Toggle Bit Timing Diagram Address A18-0 #WE #CE #OE DQ6 T OEH W39L040A T OES Publication Release Date: April 14, 2005 Revision A3 ...
Page 22
... TIME PART NO. (nS) W39L040AP70B 70 W39L040AP90B 90 W39L040AQ70B 70 W39L040AQ90B 90 W39L040AT70B 70 W39L040AT90B 90 W39L040A70B 70 W39L040A90B 90 W39L040AT70Z 70 W39L040AT90Z 90 W39L040AP70Z 70 W39L040AP90Z 90 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
Page 23
HOW TO READ THE TOP MARKING Example: The top marking of 32-pin TSOP W39L040AT-70 W39L040AT70B 2138977A-A12 325OBFA st 1 line: Winbond logo nd 2 line: the part number: W39L040AT70B rd 3 line: the lot number th 4 line: the ...
Page 24
... Notes: 1. Dimensions D & not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. ...
Page 25
TSOP ( mm 0.10(0.004) b θ 11.4 32L STSOP ( mm θ ...
Page 26
VERSION HISTORY VERSION DATE A1 Sep. 24, 2004 A2 Nov. 25, 2004 A3 April 14,2005 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control ...