H5PS1G63EFR-20L HYNIX [Hynix Semiconductor], H5PS1G63EFR-20L Datasheet
H5PS1G63EFR-20L
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H5PS1G63EFR-20L Summary of contents
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... DDR2 SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/ Oct. 2008 H5PS1G63EFR H5PS1G63EFR 1 ...
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... Operating temperature condition changed. 62 IDD Value(-20L) inserted. 1.0 56 Thermal resistance value inserted. 1.1 69 Typo corrected. (500Mhz tWR Value) Note) The H5PS1G63EFR data sheet follows all of JEDEC DDR2 standard. Rev. 1.1/Oct. 2008 History H5PS1G63EFR Date Remark May. 2008 Preliminary Preliminary Jul. 2008 Jul. 2008 Preliminary Aug ...
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... Auto Precharge Operation 2.7 Refresh Commands 2.7.1 Auto Refresh Command 2.7.2 Self Refresh Command 2.8 Power Down 2.9 Asynchronous CKE Low Event 2.10 No Operation Command 2.11 Deselect Command 3. Truth Tables 3.1 Command Truth Table 3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors 3.3 Data Mask Truth Table Rev. 1.1/ Oct. 2008 H5PS1G63EFR 3 ...
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... AC Input Test Conditions 5.2.4 Differential Input AC Logic Level 5.2.5 Differential AC Output Parameters 5.3 Output Buffer Levels 5.3.1 Output AC Test Conditions 5.3.2 Output DC Current Drive 5.3.3 OCD default characteristics 5.4 IDD Specifications & Measurement Conditions 5.5 Input/Output Capacitance 5.6 Overshoot / Undershoot specification 6. Electrical Characteristics & AC Timing Specifications 7. Package Dimensions Rev. 1.1/ Oct. 2008 H5PS1G63EFR 4 ...
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... Self-Refresh High Temperature Entry • Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C<Tcase<95°C 1.1.2 Ordering Information Part No. Power Supply H5PS1G63EFR-20L VDD/VDDQ=1.8V H5PS1G63EFR-25C Note) Above Hynix P/N’s are Lead-free, RoHS Compliant and Halogen-free. Rev. 1.1/Oct. 2008 Clock ...
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... VSSQ J VREF VSS WE K CKE L BA1 BA0 NC, A14 A12 R ROW AND COLUMN ADDRESS TABLE ITEMS H5PS1G63EFR VSSQ UDQS VDDQ UDQS VSSQ DQ15 VDDQ DQ8 VDDQ DQ10 VSSQ DQ13 VSSQ LDQS VDDQ LDQS VSSQ DQ7 VDDQ DQ0 ...
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... In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMR(1) x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMR(1) x16 LDQS and UDQS No Connect : No internal electrical connection is present. DQ Power Supply : 1.8V +/- 0.1V DQ Ground DLL Power Supply : 1.8V +/- 0.1V DLL Ground Power Supply : 1.8V +/- 0.1V Ground Reference voltage. H5PS1G63EFR DESCRIPTION 7 ...
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... ACT CKEH Activating CKEL CKEH CKEL Bank Active Read Write WRA RDA Read RDA PR, PRA PR, PRA PR, PRA Precharging H5PS1G63EFR CKEL Self REF Refreshing CKEL Precharge Power Down CKEL Automatic Sequence Command Sequence Read Reading RDA Reading with Autoprecharge CKEL = CKE low, enter Power Down ...
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... At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ). If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of Rev. 1.1/ Oct. 2008 H5PS1G63EFR * low state (all other inputs *2 ...
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... MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. Rev. 1.1/ Oct. 2008 PRE MRS REF ALL tRP tMRD tRFC tMRD min. 200 Cycle DLL RESET H5PS1G63EFR MRS EMRS REF tRFC tMRD Follow OCD Flowchart OCD Default ANY EMRS CMD tOIT OCD CAL ...
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... XARD XARDS MRS /CAS Latency WR=4 H5PS1G63EFR /CAS Latency BT Burst Length Burst Length A Burst Type 3 0 Sequential A 1 Interleave 0 0 CAS Latency * WR(cycles Reserved ...
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... DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for syn- chronization to occur may result in a violation of the tAC or tDQSCK parameters. Rev. 1.1/ Oct. 2008 H5PS1G63EFR 12 ...
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... A6 A2 MRS 0 0 ODT Disabled EMRS( EMRS( OCD Calibration Program OCD Calibration mode exit; maintain setting Drive(1) Drive(0) a Adjust mode OCD Calibration default Qoff H5PS1G63EFR Rtt Additive latency Rtt D.I.C A DLL Enable NOMINAL 0 Enable 1 Disable ...
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... SRF 0* High Temp Self-refresh Rate Enable Disable 2 Enable(Optional)* A3 DCC Enable(Optional)* Full Array Half Array (BA[2:0]=000,001,010&011) Quarter Array (BA[2:0]=000&001) 1/8th Array (BA[2:0]=000) Half Array (BA[2:0]=100,101,110&111) Quarter Array (BA[2:0]=110&111) 1/8th Array (BA[2:0]=111) H5PS1G63EFR PASR*3 0* DCC*3 Disable ...
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... EMR(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization. Figure 6. EMR(3) programming Rev. 1.1/ Oct. 2008 H5PS1G63EFR Address Field Extended Mode Register(2) 15 ...
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... EMRS: OCD calibration mode exit Rev. 1.1/ Oct. 2008 EMRS: OCD calibration mode exit ALL OK ALL OK EMRS: OCD calibration mode exit End H5PS1G63EFR EMRS: Drive(0) DQ & DQS Low; DQS High Test Need Calibration EMRS: OCD calibration mode exit EMRS : Enter Adjust Mode ...
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... NOP 0 NOP 1 Increase by 1 step 0 Decrease by 1 step 1 Increase by 1 step 0 Decrease by 1 step H5PS1G63EFR Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step ...
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... DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0) DQS DQ tOIT Rev. 1.1/ Oct. 2008 NOP NOP DQS tDS tDH NOP NOP DQs high for Drive(1) DQs low for Drive(0) H5PS1G63EFR OCD calibration mode exit EMRS NOP NOP WR OCD calibration mode exit NOP EMRS tOIT NOP Hi-Z 18 ...
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... Selection between sw1 or sw2 is determined by “Rtt (nominal)” in EMRS Termination included on all DQs, DM, DQS, DQS pins. Target Rtt (ohm) = (Rval1 (Rval2 Rev. 1.1/ Oct. 2008 sw1 sw2 Rval2 Rval1 Rval1 Rval2 sw1 sw2 H5PS1G63EFR Input Pin 19 ...
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... ODT Internal Term Res. ODT timing for powerdown mode CKE t IS ODT Internal Term Res. t AONPD,min t AONPD,max Rev. 1.1/ Oct. 2008 AOFD t AOND t AON,min t AON,max AOFPD,min H5PS1G63EFR AOF,min t AOF,max AOFPD,max ...
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... T-3 T-2 T ANPD AOFD RTT AOFPDmax RTT AOND AONPDmax H5PS1G63EFR Active & Standby mode timings to be applied. Power Down mode timings to be applied. Active & Standby mode timings to RTT be applied. Power Down mode timings to be applied. ...
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... Rev. 1.1/ Oct. 2008 AXPD ODT Internal Term Res ODT Internal RTT Term Res. ODT Internal Term Res ODT Internal Term Res. H5PS1G63EFR T8 T9 T10 T11 AOFD RTT t AOFPDmax AOND RTT t AONPDmax RTT 22 ...
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... Row Addr CCD additive latency delay ( ) AL Read Begins > RRD Bank B Bank Post CAS Activate Read (>= t Bank Active ) RAS RAS Cycle time ( H5PS1G63EFR Tn Tn+1 Tn+2 Bank A Bank B Addr. Addr. Bank A Bank B Precharge Precharge >= t Bank Precharge time ( ) RP > Tn+3 Bank A Row Addr. ...
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... setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Rev. 1.1/ Oct. 2008 H5PS1G63EFR respectively. The minimum CAS to 24 ...
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... Rev. 1.1/ Oct. 2008 Write A-Bank > = tRAC Read A-Bank > = tRAC H5PS1G63EFR Dout3 Din1 Din3 Dout0 Dout1 Dout2 Din0 Din2 Write A-Bank Din1 ...
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... H5PS1G63EFR Interleave Addressing (decimal ...
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... NOP READ A DQS/DQS DQs Rev. 1.1/ Oct. 2008 RPRE DQSQmax t QH Figure YY-- Data output (read) timing NOP NOP NOP H5PS1G63EFR t RPST DQSQmax NOP NOP NOP =< t DQSCK DOUT A DOUT A DOUT A DOUT ...
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... NOP NOP NOP =< t DQSCK DOUT A DOUT A DOUT Tn-1 Tn Tn+1 Post CAS NOP NOP WRITE A t (Read to Write turn around time) RTW DOUT A DOUT A 0 H5PS1G63EFR NOP NOP NOP DOUT A DOUT A DOUT A DOUT A DOUT Tn+2 Tn+3 Tn+4 NOP NOP NOP ...
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... The seamless burst read operation is supported by enabling a read command at every other clock for operation, and every 4 clock for operation. This operation is allowed regardless of same or different banks as long as the banks are activated. Rev. 1.1/ Oct. 2008 Post CAS NOP NOP READ H5PS1G63EFR NOP NOP NOP DOUT A DOUT B DOUT A DOUT A DOUT A 0 ...
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... For example, Minimum Read to Precharge timing BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Rev. 1.1/ Oct. 2008 NOP NOP NOP H5PS1G63EFR NOP NOP NOP NOP 30 ...
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... DQSL DQS DQS t WPRE DMin DMin Data input (write) timing NOP NOP NOP < DQSS DIN A DIN A 0 H5PS1G63EFR t WPST DMin DMin NOP NOP NOP Completion of the Burst Write > DIN A DIN ...
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... DQSS the Burst Write DIN A DIN A DIN A DIN Post CAS NOP READ > = tWTR DIN A DIN A DIN H5PS1G63EFR NOP Precharge NOP > = tRP > NOP NOP NOP Bank A Activate T8 T9 NOP DOUT A ...
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... operation. This operation is allowed regardless of same or different banks as long as the banks are activated Rev. 1.1/ Oct. 2008 Post CAS NOP NOP Write B DQS DQS DIN A DIN H5PS1G63EFR NOP NOP NOP DIN B DIN B DIN B DIN B DIN A DIN ...
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... For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end. Rev. 1.1/ Oct. 2008 Write B NOP NOP H5PS1G63EFR NOP NOP NOP NOP ...
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... and x16 bit organization is not used during read cycles. Data Mask Timing DQS/ DQS DQ DM Data Mask Function, WL=3, AL= shown Case 1 : min t DQSS CK CK Write COMMAND DQS/DQS DQ DM Case 2 : max t DQSS DQS/DQS DQ DM Rev. 1.1/ Oct. 2008 DQSS t DQSS H5PS1G63EFR ...
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... LOW LOW HIGH HIGH LOW HIGH HIGH DON’T CARE DON’T CARE ). A precharge command cannot be issued until t RP H5PS1G63EFR Precharged Bank(s) Remarks Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only 1Gb and higher Bank 5 only 1Gb and higher ...
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... DOUT A DOUT A 0 > RAS > RTP <= 2 clocks RTP NOP NOP NOP DOUT A DOUT A 0 > RTP H5PS1G63EFR Bank A NOP NOP Active > DOUT A DOUT NOP NOP Precharge A DOUT A DOUT A ...
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... Precharge A NOP NOP > RAS > RTP <= 2 clocks RTP Precharge A NOP NOP > > RAS > RTP H5PS1G63EFR Bank A NOP NOP Activate > DOUT A DOUT A DOUT A DOUT Bank A NOP ...
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... Rev. 1.1/ Oct. 2008 > 2 clocks RTP NOP NOP NOP DOUT A DOUT A 0 > RAS > RTP second 4-bit prefetch H5PS1G63EFR NOP NOP Precharge A > DOUT A DOUT A DOUT A DOUT A DOUT ...
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... T3 T4 NOP NOP NOP DIN A DIN A DIN A DIN NOP NOP NOP DIN A DIN H5PS1G63EFR NOP NOP NOP Completion of the Burst Write > NOP NOP NOP Completion of the Burst Write > DIN A DIN ...
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... A new bank activate (command) may be issued to the same bank if the following two conditions are satis- fied simultaneously. (1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. Rev. 1.1/ Oct. 2008 H5PS1G63EFR 41 ...
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... RL =4 DOUT A DOUT A 0 > RTP t RTP > 2 clocks RTP NOP NOP NOP DOUT A DOUT RTP Precharge begins here H5PS1G63EFR NOP NOP NOP > DOUT A DOUT A DOUT A DOUT A DOUT Precharge begins here ...
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... Rev. 1.1/ Oct. 2008 NOP NOP NOP Auto Precharge Begins > NOP NOP NOP Auto Precharge Begins > H5PS1G63EFR <= 2 clocks) RTP NOP NOP NOP > DOUT A DOUT A DOUT A DOUT <= 2 clocks) RTP T5 ...
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... DIN A DIN A DIN A DIN NOP NOP NOP Completion of the Burst Write DIN A DIN A DIN A DIN H5PS1G63EFR NOP NOP NOP Auto Precharge Begins > > > NOP NOP NOP Auto Precharge Begins > > ...
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... Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self Refresh operation. Rev. 1.1/ Oct. 2008 T2 T3 > RFC REF NOP H5PS1G63EFR Tm Tn > RFC REF NOP ANY ...
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... Read or a Read with autoprecharge command - tXSNR is applied for any command except a Read or a Read with autoprecharge command. Rev. 1.1/ Oct. 2008 tRP* tIS tAOFD tIS tIH Self Refresh H5PS1G63EFR Tm Tn > = tXSNR > = tXSRD tIS Valid NOP NOP NOP 46 ...
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... Basic Power Down Entry and Exit timing diagram CK/ CKE VALID NOP Command t CKE Enter Power-Down mode Rev. 1.1/ Oct. 2008 NOP t CKE Exit Power-Down mode H5PS1G63EFR VALID VALID VALID t t XP, XARD, t XARDS t CKE IH Don’t Care 47 ...
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... AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied Tx+1 Tx+2 Tx+3 Start internal precharge PRE AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied H5PS1G63EFR Tx+4 Tx+5 Tx+6 Tx+7 Tx+4 Tx+5 Tx+6 Tx Tx+4 Tx+5 Tx+6 Tx+7 CKE should be kept high until the end of burst operation. Tx+4 Tx+5 Tx+6 Tx+7 CKE should be kept high until the end of burst operation. ...
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... CK CK CMD WRA BL=4 CKE DQ DQS DQS CMD WRA BL=8 CKE DQ DQS DQS Rev. 1.1/ Oct. 2008 Tm+1 Tm+2 Tm tWTR Tm+1 Tm+2 Tm+3 Tm Tm+1 Tm+2 Tm WR*1 Tm+1 Tm+2 Tm+3 Tm H5PS1G63EFR Tx+1 Tx+2 Ty Ty+1 Tm+5 Tx Tx+1 Tx+2 D tWTR Tx+1 Tx+2 Tx+3 Tx+4 PRE Tm+5 Tx Tx+1 Tx+2 PRE D WR programmed through MRS Ty+2 Ty+3 Tx+3 Tx+4 Tx+5 Tx+6 Tx+3 Tx+4 49 ...
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... CKE Precharge/Precharge all command to power down entry PR or CMD PRA CKE MRS/EMRS command to power down entry CMD MRS or EMRS CKE tMRD Rev. 1.1/ Oct. 2008 CKE can go to low one clock after a Precharge or Precharge all command H5PS1G63EFR T10 T11 50 ...
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... DRAM is ready for normal operation after the ini- tialization sequence. See AC timing parametric table for tDelay specification tCK CK# CK tDelay CKE CKE asynchronously drops low Rev. 1.1/ Oct. 2008 Stable clocks Clocks can be turned off after this point H5PS1G63EFR 51 ...
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... NOP CKE ODT tRP tAOFD Minmum 2 clocks required before changing frequency Rev. 1.1/ Oct. 2008 T4 Tx Tx+1 Ty Ty+1 Frequency Change Occurs here Stable new clock before power down exit H5PS1G63EFR Ty+2 Ty+3 Ty+4 Tz DLL NOP NOP NOP Valid RESET 200 Clocks tXP ODT is off during DLL RESET 52 ...
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... Deselect Command The Deselect command performs the same function Operation command. Deselect command occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don’t cares. Rev. 1.1/ Oct. 2008 H5PS1G63EFR 53 ...
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... H5PS1G63EFR BA0 CAS WE BA1 A15-A11 A10 BA2 Code ...
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... DESELECT or NOP L REFRESH H Refer to the Command Truth Table (200 clocks) is satisfied. XSRD DM DQs L Valid H X H5PS1G63EFR 3 3 Action (N) Maintain Power-Down Power Down Exit Maintain Self Refresh Self Refresh Exit Active Power Down Entry Precharge Power Down Entry Self Refresh Entry Note 1 ...
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... Theta_JC case surface is defined as the “outside surface of the package (case) closest to the chip mounting area when that same surface is properly hear sunk” minimize temperature variation across that surface. 7. Test condition : Voltage 1.8V / Frequency : 400Mhz Rev. 1.1/Oct. 2008 H5PS1G63EFR Rating - ...
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... V (ac) to test pin separately, then measure current I (ac), and VDDQ values defined in SSTL_18 IL V (ac (ac Rtt(eff) = I(V (ac delta 100% VDDQ H5PS1G63EFR Units Max. 1.9 V 1.9 V 1.9 V 0.51*VDDQ mV VREF+0.04 V MIN NOM MAX UNITS NOTES ohm 120 150 ...
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... Figure : AC Input Test Signal Waveform> Rev. 1.1/Oct. 2008 Min. VREF + 0.125 - 0.3 Min. VREF + 0.250 - Condition Input reference voltage to V max for falling edges as shown in the figure below. IL(ac) delta max IL(ac) H5PS1G63EFR Max. Units VDDQ + 0.3 V VREF - 0.125 V Max. Units - V VREF - 0.250 V Value Units 0 DDQ 1 ...
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... VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Rev. 1.1/Oct. 2008 Min. 0.5 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V DDQ SSQ < Differential signal levels > Min. 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 H5PS1G63EFR Max. Units Notes VDDQ + 0 Crossing point Max. Units Notes V ...
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... V OUT DDQ OH /I must be less than 21 ohm for values of V OUT OL TT are based on the conditions given in Notes 1 and 2. They are used to test min plus a noise margin and V IH H5PS1G63EFR SSTL_18 Class II Units V + 0.603 0.603 ...
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... DRAM output slew rate specification applies to 400Mhz speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Rev. 1.1/Oct. 2008 Parameter Min - 0 0 Sout 1.5 VTT 25 ohms Reference point H5PS1G63EFR Nom Max Unit Notes - - ohms 1 1.5 ohms 6 4 ohms 1,2,3 ...
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... IDD4W IDD4R IDD5 IDD6 Normal IDD7 (1KB) Rev. 1.1/Oct. 2008 25C 20L 400Mhz 500Mhz 95 105 120 130 230 300 215 250 170 180 10 10 290 300 H5PS1G63EFR Units ...
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... RCD = 1* t CK(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions Rev. 1.1/ Oct. 2008 Conditions Fast PDN Exit MR(12 Slow PDN Exit MR(12 H5PS1G63EFR Units ...
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... SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.1/ Oct. 2008 H5PS1G63EFR 64 ...
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... Input/output capacitance delta, DQ, DM, DQS, DQS Rev. 1.1/Oct. 2008 25C 20L 2 70k 70k 15 15 127.5 127.5 400/500Mhz Symbol Min CCK 1.0 CDCK x CI 1.0 CDI x CIO 2.5 CDIO x H5PS1G63EFR Units tCK Units Max 2.0 pF 0.25 pF 1.75 pF 0.25 pF 3 ...
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... V DDQ Volts (V) V SSQ Figure 2: AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins Rev. 1.1/Oct. 2008 Maximum Amplitude Maximum Amplitude Time (ns) Maximum Amplitude Maximum Amplitude Time (ns) H5PS1G63EFR Specification 0.9V 0.9V 0.45 V-ns 0.45 V-ns Overshoot Area Undershoot Area Specification 0.9V 0.9V 0.23 V-ns 0.23 V-ns Overshoot Area Undershoot Area ...
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... Power and ground clamps are required on the following input only pins: 1. BA0-BA2 2. A0-A12 3. RAS 4. CAS ODT 8. CKE V-I Characteristics table for input only pins with clamps Voltage across clamp(V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Rev. 1.1/ Oct. 2008 Minimum Power Clamp Current (mA 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0 H5PS1G63EFR Minimum Ground Clamp Current (mA 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0 67 ...
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... Refer to Specific Notes 3. Rev. 1.1/ Oct. 2008 = 1.8 +/- 0.1V) DD Symbol tRFC 0 ℃≤ T CASE tREFI 85 ℃≤ T CASE 400Mhz 300Mhz min min 6-6-6 5-5 H5PS1G63EFR 1Gb Units Notes 127 ≤ 85℃ 7 ≤ 95℃ 3.9 us 200Mhz 100Mhz min min 3-3-3 3-2 ...
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... WR+tnRP - H5PS1G63EFR 25C Unit min max -400 +400 ps -350 +350 ps 0.45 0.55 tCK(avg) 0.45 0.55 tCK(avg) min(tCL(abs tCH(abs)) 2500 8000 125 - ps 0.6 - tCK(avg) 0.35 - tCK(avg) - tAC max ps tAC min tAC max ...
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... H5PS1G63EFR 25C Unit min max 7 7.5 ns tRFC + 10 ns 200 - nCK 2 - nCK 2 nCK nCK 3 nCK 2 2 nCK tAC(max) tAC(min) ns +0.7 ...
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... Output slew rate is characterized under the test conditions as shown below. VDDQ DUT Rev. 1.1/Oct. 2008 DQ DQS Output DQS RDQS Timing RDQS reference point AC Timing Reference Load DQ Output DQS, DQS RDQS, RDQS Test point Slew Rate Test Load H5PS1G63EFR DDQ Ω DDQ Ω ...
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... D V (ac (ac) IH DMin DMin V (ac) IL Figure -- Data input (write) timing RPRE Q t DQSQmax t QH Figure -- Data output (read) timing H5PS1G63EFR t WPST V (dc (dc (dc) IH DMin DMin V (dc RPST DQSQmax ...
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... H5PS1G63EFR 1.6 V/ns 1.4 V/ns 1.2 V/ns △ △ △ △ △ tDH tDS tDH tDS tDH - - - - - - - - - - - - - -59 ...
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... Vss Delta TF Setup Slew Rate V = Falling Signal Rev. 1.1/ Oct. 2008 nominal slew rate Delta TR (dc)-V (ac)max Setup Slew Rate REF IL Rising Signal Delta TF H5PS1G63EFR nominal slew rate REF region V (ac)min-V (dc) REF IH = Delta TR 74 ...
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... Setup Slew Rate = Falling Signal Rev. 1.1/ Oct. 2008 nominal line Tangent line Delta TR Setup Slew Rate Tangent line[V = Rising Signal (dc)-V (ac)max] REF IL Delta TF H5PS1G63EFR tangent line REF region (ac)min-V (dc)] REF IH Delta TR 75 ...
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... Hold Slew Rate = Rising Signal Rev. 1.1/ Oct. 2008 REF nominal slew rate Delta TR V (dc)-V (dc)max Hold Slew Rate REF IL Falling Signal Delta TR H5PS1G63EFR nominal slew rate Delta TF V (dc)min - V (dc) IH REF = Delta TF 76 ...
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... Tangent line[V = Rising Signal Rev. 1.1/ Oct. 2008 REF Tangent line Delta TR (dc)-V (ac)max] REF IL Delta TR Hold Slew Rate Falling Signal H5PS1G63EFR nominal line tangent line nominal line Delta TF Tangent line[V (ac)min Delta TF (dc)] REF ...
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... Hold(tIH) nominal slew rate for a falling signal is defined as the REF (dc). If the actual signal is always later than the nominal slew rate REF (dc) region’, use nominal slew rate for derating value(see Fig.c) If the actual H5PS1G63EFR 1.0 V/ns △ tIS △ tIH ...
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... Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measure- ment points are not critical as long as the calculation is consistenet. Rev. 1.1/ Oct. 2008 H5PS1G63EFR 79 ...
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... Fine Pitch Ball Grid Array Outline A1 BALL MARK < Top View> 84X Φ0.45 ± 0.05 < Bottom View> Rev. 1.1/ Oct. 2008 8.00 ± 0.10 0. 6.40 2.10 ± 0.10 A1 BALL MARK 0.80 1.60 1.60 H5PS1G63EFR 2-R0.13MAX < SIDE View> 1.10 ± 0.10 0.34 ± 0.05 Note: All dimensions are in millimeters. 80 ...