GM71CS17403C Hynix Semiconductor, GM71CS17403C Datasheet
GM71CS17403C
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GM71CS17403C Summary of contents
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Description The GM71C(S)17403C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71C(S)17403C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)17403C/CL offers Extended Data Out (EDO) Mode as ...
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Pin Description Pin A0-A10 Address Inputs A0-A10 Refresh Address Inputs I/O1-I/O4 Data-input/Data-output RAS Row Address Strobe CAS Column Address Strobe Ordering Information Type No. GM71C(S)17403CJ/CLJ-5 GM71C(S)17403CJ/CLJ-6 GM71C(S)17403CJ/CLJ-7 GM71C(S)17403CT/CLT-5 GM71C(S)17403CT/CLT-6 GM71C(S)17403CT/CLT-7 Absolute Maximum Ratings* Symbol T Ambient Temperature under Bias A ...
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DC Electrical Characteristics (V Symbol V Output Level OH Output "H" Level Voltage (I V Output Level OL Output "L" Level Voltage (I Operating Current I CC1 Average Power Supply Operating Current (RAS, CAS Cycling Standby Current (TTL) I CC2 ...
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Capacitance (V = 5V+/-10 Symbol C Input Capacitance (Address Input Capacitance (Clocks Output Capacitance (Data-In/Out) I/O Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = V to disable ...
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Read Cycle Symbol Parameter t Access Time from RAS RAC t Access Time from CAS CAC t Access Time from Address AA t Access Time from OE OAC t Read Command Setup Time RCS t Read Command Hold Time to ...
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Write Cycle Symbol Parameter Write Command Setup Time t WCS Write Command Hold Time t WCH Write Command Pulse Width Write Command to RAS Lead Time RWL t Write Command to CAS Lead Time CWL Data-in Setup ...
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EDO Page Mode Cycle Symbol Parameter t EDO Page Mode Cycle Time HPC EDO Page Mode RAS Pulse Width t RASP Access Time from CAS Precharge t ACP t RAS Hold Time from CAS Precharge RHCP t Output data Hold ...
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Notes Measurements assume initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before- RAS refresh). If the internal refresh ...
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In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset impedance <=t OEH CWL 19. The 16M DRAM offers a 16-bit time saving ...
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Package Dimension 24(26) SOJ 0.661(16.80) MIN 0.669(17.00) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 24(26) TSOP (TYPE II) 0.670(17.04) MIN 0.678(17.24) MAX 0.012(0.30) MIN 0.020(0.50) MAX Rev 0.1 / Apr’01 0.128(3.25) MIN 0.147(3.75) MAX 0.026(0.66) MIN 0.032(0.81) MAX 0.037(0.95) MIN ...