ICX224 SONY [Sony Corporation], ICX224 Datasheet - Page 48

• Manufacturer Part Number: ICX224
• Description: Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
• Manufacturer: SONY [Sony Corporation]

Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
3. Separate the timing generator block V
4. The difference in potential between the timing generator block V
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
6. Do not perform serial communication with the CCD signal processor block during the effective image
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block V
block DV
before or at the same time as the VH pin power supply is started up.
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
block DV
Also, the ADC output driver stage is connected to the dedicated power supply pin DV
pin from other power supplies is recommended to avoid affecting the internal analog circuits.
signal processor block DV
2 V
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block V
V
AV
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
SS5
SS5
DD
, V
f and 3 V
and AV
SS6
DD1
DD1
and VM and the CCD signal processor block DV
, DV
, DV
SS6
DD
DD2
g should be 0.1V or less.
DD2
should be 0.1V or less.
t1
t2
, AV
, AV
t2
DD1
t1
DD1
DD1
, AV
20%
20%
, AV
, DV
DD2
DD2
DD2
, AV
, AV
, AV
DD1
DD3
DD3
DD1
, V
, AV
, AV
DD2
, AV
DD1
DD4
DD4
, V
, V
DD2
– 48 –
and AV
DD3
DD2
and AV
, AV
, V
, V
DD3
DD4
DD5
DD3
DD5
SS1
, AV
, V
and V
pins.
, DV
pin power supplies at the same time either
DD4
DD4
DD4
DD5
SS2
and V
pin supply voltage 3 V
and AV
, DV
pins from the CCD signal processor
DD5
SS3
DD5
pin and CCD signal processor
, AV
pin supply voltages 1 V
SS1
15.0V
0V
–7.5V
, AV
SS1
DD1
, V
SS2
DD
. Separating this
SS2
, AV
c and the CCD
, V
SS3
CXD3410GA
SS3
, AV
, V
DD
SS4
SS4
e,
,
,