HT48RA0-5_12 HOLTEK [Holtek Semiconductor Inc], HT48RA0-5_12 Datasheet
HT48RA0-5_12
Related parts for HT48RA0-5_12
HT48RA0-5_12 Summary of contents
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... One programmable carrier output - using 9-bit timer Carrier output pin (REM) General Description The HT48RA0-5 is 8-bit high performance, RISC archi- tecture microcontroller device specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibil- ity, timer functions, watchdog timer, HALT and wake-up Rev ...
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... REM pin is a high sink current NMOS open drain carrier output pin which will floating condition after a reset. The selection of REM or REMDRV is determined by a configuration option. Positive power supply Negative power supply, ground 2 HT48RA0-5 August 13, 2012 ...
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... No load, system HALT, 3V WDT disable No load, system HALT, 3V WDT enable =0. =0. =0. =0.2V 3V 300 100 1.8 0.035 3 HT48RA0-5 Ta=25 C Typ. Max. Unit 3.6 V 3.6 V 0.5 1.2 mA 0.1 1.0 A 5 1.2 mA 350 mA 150 200 k 1.9 2 ...
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... Test Conditions Min. V Conditions DD 1.8V~ 400 Ta= - 3.6V 2.2V~ Ta= - 4013 3.6V Power-up or wake-up from HALT 3V 45 0.25 1 Test Conditions Min. V Conditions DD 0.035 1 4 HT48RA0-5 Ta=25 C Typ. Max. Unit 4000 kHz 4095 4179 kHz t 1024 SYS 90 180 s 1.00 2. Typ. Max. Unit 100 mV V/ms ms August 13, 2012 ...
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... Characteristics Curves Rev.1.50 5 HT48RA0-5 August 13, 2012 ...
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... When a control transfer takes place, an additional dummy cycle is required. Execution Flow Program Counter * Program Counter + Program Counter S9~S0: Stack register bits @7~@0: PCL bits 6 HT48RA0 August 13, 2012 ...
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... Bit undefined and reading will return the result 1 . Any writing operation to MP will only transfer the lower 7-bits of data to MP. Table Location * Table Location @7~@0: Table pointer bits 7 HT48RA0 August 13, 2012 ...
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... The TO and PDF flags can only be changed by the Watchdog Timer overflow, device power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. Function Status (0AH) Register 8 HT48RA0-5 August 13, 2012 ...
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... Note that if this internal system clock option is selected requires no ex- ternal pins for its operation, I/O pins PB5 and PB6 are free for use as normal I/O pins HT48RA0 8pF 10pF HIRC August 13, 2012 ...
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... Once a wake-up event(s) occurs, it takes 1024 t (system clock periods) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Watchdog Timer 10 HT48RA0-5 SYS August 13, 2012 ...
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... Points to the top of the stack Low level state or floating Carrier output state* * Determined by configuration option Note recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise is significant. External RES Circuit 11 HT48RA0-5 August 13, 2012 ...
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... CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each line of the I/O ports has a wake-up capability when the relevant pin is configured as an input line. 12 HT48RA0-5 WDT Time-out (HALT)* 000H -uuu uuuu uuuu uuuu ...
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... TSR1 and TSR0 to the Down Coun- ter is completed and then wait until TSR1.1 is set by user. Setting TSR1.1=1, the timer will start counting. The timer will stop when its count is equal to 0 and then TOEF is set equal HT48RA0-5 01H, t8 August 13, 2012 ...
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... Setting the t9 bit channels the timer to the REM pin. The =64/f ] REM pin will be a combination of the timer and carrier sig- SYS nals. Note: The carrier output results if bit 9 of the high-level period setting modulo register (CARH) is cleared ( 0 ). Timer Output when Carrier is not Output SYS Timer Configuration 14 HT48RA0-5 SYS August 13, 2012 ...
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... Configuration of Remote Controller Carrier Generator Note: 1. Bit 9 of the modulo register for setting the low-level period (CARL) is fixed t9: Flag that enables timer output (timer block, see Timer Configuration) Rev.1.50 Bit5 Bit4 Bit3 Bit2 CL. CL. CL.3 CL.2 CH.5 CH.4 CH.3 CH.2 15 HT48RA0-5 Bit1 Bit0 CL.1 CL.0 CL.8 Fix 0 CH.1 CH.0 CH.9 CH.8 (CARY) = 4MHz. SYS August 13, 2012 ...
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... When the carrier signal is active and during the time when the signal is high, if the timer output should go low, the carrier signal will first complete its high level period before going low. Rev.1. SYS SYS 45H 16 HT48RA0-5 August 13, 2012 ...
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... SYS t (ms) t (ms) t (ms 9.256 18.510 27.770 8.770 17.540 26.310 5.950 11.900 17.850 =4095kHz) SYS 17 HT48RA0-5 REMDRV Function (NMOS Output) Floating output 64/f SYS (with carrier output) Carrier output Floating output Low-level output f (kHz) Duty C 60.60 1/2 38.10 1/3 37.90 1/3 36.00 1/3 f (kHz) Duty C 36 1/3 38 1/3 56 ...
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... To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system clock pulses before entering normal operation. *2 Since low voltage has to be maintained in its original state and exceed 1ms, a 1ms delay enters the reset mode. Rev.1.50 The relationship between V Low Voltage Reset 18 HT48RA0-5 and V is shown below. DD LVR August 13, 2012 ...
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... WDT function: enable or disable 5 CLRWDT instruction selections instructions 6 WDT time-out period selections: 2 LVR Options 7 LVR function: enable or disable Reset Pin Options 8 I/O or RES pin selection Rev.1.50 Code Option : SYS / HT48RA0-5 August 13, 2012 ...
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... Application Circuits Note: The 0.1uF capacitor is required to ensure that the system clock frequency meets with the specified tolerance in the A.C. Characteristics. Rev.1.50 20 HT48RA0-5 August 13, 2012 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 21 HT48RA0-5 August 13, 2012 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 22 HT48RA0-5 Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev.1.50 Description 23 HT48RA0-5 Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev.1.50 24 HT48RA0-5 August 13, 2012 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev.1.50 addr 25 HT48RA0-5 August 13, 2012 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev.1. HT48RA0-5 August 13, 2012 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev.1.50 addr 27 HT48RA0-5 August 13, 2012 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev.1.50 Stack Stack Stack [m]. 0~6) 28 HT48RA0-5 August 13, 2012 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev.1.50 [m]. 0~6) 29 HT48RA0-5 August 13, 2012 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev.1.50 [ HT48RA0-5 August 13, 2012 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev.1.50 0 [m] [ HT48RA0-5 August 13, 2012 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev.1.50 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 32 HT48RA0-5 August 13, 2012 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev.1.50 33 HT48RA0-5 August 13, 2012 ...
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... Symbol Symbol Rev.1.50 Dimensions in inch Min. Nom. 0.228 0.150 0.012 0.386 0.050 0.004 0.016 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.30 9.80 1.27 0.10 0.41 0. HT48RA0-5 Max. 0.244 0.157 0.020 0.394 0.069 0.010 0.050 0.010 8 Max. 6.20 3.99 0.51 10.01 1.75 0.25 1.27 0.25 8 August 13, 2012 ...
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... Symbol Rev.1.50 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.335 0.049 0.025 0.004 0.015 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 8.51 1.24 0.64 0.10 0.38 0. HT48RA0-5 Max. 0.244 0.158 0.012 0.347 0.065 0.010 0.050 0.010 8 Max. 6.20 4.01 0.30 8.81 1.65 0.25 1.27 0.25 8 August 13, 2012 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 20S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev.1.50 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 36 HT48RA0-5 August 13, 2012 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev.1.50 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 Dimensions in mm +0.3/-0.1 16.0 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 9.0 0.1 2.3 0.1 0.30 0.05 13.3 0.1 37 HT48RA0-5 August 13, 2012 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev.1.50 38 HT48RA0-5 August 13, 2012 ...