HT48RA0-5_12 HOLTEK [Holtek Semiconductor Inc], HT48RA0-5_12 Datasheet - Page 10

• Manufacturer Part Number: HT48RA0-5_12
• Description: Remote Type 8-Bit OTP MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Watchdog Timer - WDT
The WDT clock source is implemented by the instruction
clock which is the system clock divided by 4 or the inter-
nal RC oscillator with the frequency of 12kHz. The clock
source is processed by a frequency divider and a
prescaler to provide various time out periods.
WDT time out period =
Where n= 8~11 selected by a configuration option.
The WDT timer is designed to prevent a software mal-
function or sequence jumping to an unknown location
with unpredictable results. The Watchdog Timer can be
disabled by configuration option. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation and the WDT will lose its protection pur-
pose. In this situation the logic can only be restarted by
external logic.
A WDT overflow under normal operation will initialise a
tents of the WDT prescaler, two methods are adopted,
software instructions or a HALT instruction. There are two
types of software instructions. One type is the single in-
struction CLR WDT , the other type comprises two in-
structions, CLR WDT1 and CLR WDT2 . Of these two
types of instructions, only one can be active depending on
the configuration option
tion . If the CLR WDT is selected (i.e.. CLR WDT times
equal one), any execution of the CLR WDT instruction will
clear the WDT. In case CLR WDT1 and CLR WDT2 are
chosen (i.e.. CLR WDT times equal two), these two in-
structions must be executed to clear the WDT; otherwise,
the WDT may reset the chip due to a time-out.
Rev.1.50
chip reset and set the status bit TO . To clear the con-
Clock Source
CLR WDT times selection op-
2
n
Watchdog Timer
10
Power Down Operation - HALT
The Power-down mode is initialised by the HALT in-
struction and results in the following:
The system can quit the HALT mode by means of an ex-
ternal falling edge signal on port B. By examining the TO
and PDF flags, the reason for chip reset can be deter-
mined. The PDF flag is cleared when the system powers
up or when a CLR WDT instruction is executed and is set
when the HALT instruction is executed. The TO flag is set
if the WDT time-out occurs during normal operation.
The port B wake-up can be considered as a continuation
of normal execution. Each bit in port B can be independ-
ently selected to wake up the device by the code option.
Awakening from an I/O port stimulus, the program will
resume execution of the next instruction.
Once a wake-up event(s) occurs, it takes 1024 t
(system clock periods) to resume normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
The system oscillator turns off and the WDT stops.
The contents of the on-chip Data Memory and regis-
ters remain unchanged.
WDT prescaler is cleared.
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
HT48RA0-5
August 13, 2012
SYS