HT46CU66 HOLTEK [Holtek Semiconductor Inc], HT46CU66 Datasheet - Page 16

• Manufacturer Part Number: HT46CU66
• Description: A/D Type 8-Bit MCU with LCD
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from 2
base time-out occurs, the related interrupt request flags,
TBF; bit 5 of the MFIC register, and MFF; bit 6 of the
INTC1 register, will be set. If the interrupt is enabled,
and the stack is not full, a subroutine call to location 18H
occurs. The time base time-out signal can also be ap-
plied as a clock source for the Timer/Event Counter 1 to
obtain longer time-out periods.
Real Time Clock - RTC
The real time clock operates in the same manner as the
time base in that it is used to supply a regular internal in-
terrupt. Its time-out period ranges from f
the actual value of which is setup by software program-
ming. Writing data to the RT2, RT1 and RT0 bits in the
RTCC register, provides various time-out periods. If an
RTC time-out occurs, the related interrupt request flag,
RTF; bit 6 of the MFIC and MFF; bit 6 of the INTC1, is
set. If the interrupt is enabled, and the stack is not full, a
subroutine call to location 18H occurs. The real time
clock time-out signal can also be applied as a clock
source for Timer/Event Counter 0 in order to get longer
time-out period.
Note: * not recommended to be used
Rev. 1.20
RT2
0
0
0
0
1
1
1
1
RT1
0
0
1
1
0
0
1
1
12
/f
S
to 2
RT0
Real Time Clock
0
1
0
1
0
1
0
1
Time Base
15
/f
S
RTC Clock Divided Factor
selected by options. If a time
2
2
2
2
2
2
2
2
10
11
8
9
12
13
14
15
*
*
*
*
S
/2
8
to f
S
/2
15
,
16
Power Down Operation - HALT
The Power Down mode is initialised by the HALT in-
struction and results in the following.
The system leaves the Power Down mode by way of an
external reset, an interrupt, an external falling edge sig-
nal on port A, or a WDT overflow. An external reset
causes device initialisation, and a WDT overflow per-
forms a warm reset . After examining the TO and PDF
flags, the reason behind the chip reset can be deter-
mined. The PDF flag is cleared by a system power-up or
by executing the CLR WDT instruction, and is set by
executing the HALT instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, and
leaves the other registers in their original state.
A Port A wake-up and interrupt methods can be consid-
ered as a continuation of normal execution. Each bit in
Port A can be independently selected to wake up the de-
vice via configuration options. Awakening from an I/O
port stimulus, the program resumes execution of the
next instruction. On the other hand, awakening from an
interrupt, two sequence may occur. If the related inter-
rupt is disabled or the interrupt is enabled but the stack
is full, the program resumes execution at the next in-
struction. But if the interrupt is enabled, and the stack is
not full, the regular interrupt response takes place.
When an interrupt request flag is set before entering the
that interrupt.
If wake-up events occur, it takes 1024 t
clock period) to resume normal operation. In other
words, a dummy period is inserted after a wake-up. If a
wake-up results from an interrupt acknowledge, the ac-
tual interrupt subroutine execution is delayed by more
than one cycle. However, if a wake-up results in the next
instruction execution, the execution will be performed
immediately after the dummy period has finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Power Down
state.
HALT state, the system cannot be awakened using
The system oscillator turns off but the WDT oscillator
keeps running if the internal WDT oscillator or the real
time clock is selected.
The contents of the on-chip RAM and of the registers
remain unchanged.
The WDT is cleared and starts recounting, if the WDT
clock source comes from the WDT oscillator or the
real time clock oscillator.
All I/O ports maintain their original status.
The PDF flag is set but the TO flag is cleared.
The LCD driver keeps running, if the WDT OSC or
RTC OSC is selected.
HT46RU66/HT46CU66
October 2, 2007
SYS
(system