AN694 SILABS [Silicon Laboratories], AN694 Datasheet - Page 4

• Manufacturer Part Number: AN694
• Description: WRITING TO FLASH FROM FIRMWARE ON SiM3XXXX DEVICES
• Manufacturer: SILABS [Silicon Laboratories]

AN694
3.3. Device-Specific Notes
Various MCUs have features that require consideration when accessing Flash.
3.3.1. SiM3Cxxx, SiM3Uxxx, and SiM3Lxxx Flash Lock and Key
All SiM3Cxxx, SiM3Uxxx, and SiM3Lxxx devices' writes and erases to Flash are protected with a lock and key
function. The Flash Lock and Key Register (FLASHCTRLn) must be written with the correct key codes in sequence
before Flash operations may be performed. The key codes are: 0xA5, 0xF1 for a single write or erase operation,
and 0xA5, 0xF2 for multiple writes or erase operations. The timing does not matter, but the codes must be written
in order. If the key codes are written out of order or the wrong codes are written, Flash writes and erases will be
disabled until the next system reset. Flash writes and erases will also be disabled if a Flash write or erase is
attempted before the key codes have been written properly. For a single write or erase, the Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be performed. For
multiple writes or erases, the Flash remains unlocked until the lock sequence is written (0xA5, 0x5A); the key
codes do not need to be written before a following Flash operation can be performed.
3.3.2. SiM3Cxxx, SiM3Uxxx, and SiM3Lxxx Flash Read Timing
The SiM3Cxxx, SiM3Uxxx, and SiM3Lxxx devices require that the speed mode (SPMD) and the read-store enable
(RDSEN) bits be set appropriately, depending on the AHB frequency. In addition, the Flash read timing mode
(FLRTMD) bit can be configured to save power at slower clock frequencies. See the FLASHCTRLn chapter in the
device's reference manual for detailed information on the read timing ranges.
3.3.3. SiM3Cxxx, SiM3Uxxx, and SiM3Lxxx VDD High Threshold
The SiM3Cxxx, SiM3Uxxx, and SiM3Lxxx devices have two settings for the VDD monitor threshold: Standard and
High. The High setting increases the VDD Low (early warning) and VDD reset thresholds by approximately
300 mV. The High setting is recommended when operating at faster AHB clock speeds. See the VMONn chapter in
the device's reference manual for detailed information on enabling the High threshold.
3.4. Flash Write and Erase Operations
The basic write operation writes a single half-word to Flash. The erase operation applies to a full page of Flash.
Flash write and erase operations on Silicon Labs MCU devices are accomplished by using the WRDATA and
WRADDR registers within the FLASHCTRLn module. The setting of the ERASEEN field within the FLASHCTRLn
module determines whether a write or an erase will execute. Flash erase operations occur on page boundaries.
The erase operation sets all the bits in the Flash page to logic 1. Flash write operations, which clear bits to logic 0,
occur on single-byte boundaries. To successfully complete a write to Flash, the target bytes must be erased to
0xFFFF because the write instruction can only clear bits in a half-word.
3.5. Flash Read Operations
The basic read operation reads a single word from Flash. Flash read operations are accomplished by reading an
address within the Flash region of the device memory map. See the Memory Organization chapter in the device's
reference manual for detailed information on the Flash region boundaries.
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