VT8601 Via, VT8601 Datasheet - Page 30

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Bus 0 Registers - Host Bridge
PCI Configuration Registers
Device-Specific Configuration Registers
Revision 1.3 September 8, 1999
2D-2C Subsystem Vendor ID
3C-3D -reserved- (interrupt line & pin)
Offset Configuration Header
28-2B -reserved- (unassigned)
34-3B -reserved- (unassigned)
Offset CPU Interface Control
Offset DRAM Control
5A-5F DRAM Row Ending Address:
2F-2E Subsystem ID
3E-3F -reserved- (min gnt and max latency)
6E-6F -reserved- (unassigned)
13-10 Graphics Aperture Base
14-27 -reserved- (base address registers)
33-30 -reserved- (expan ROM base addr)
37-34 Capability Pointer
55-54 Non-Cacheable Region #1
57-56 Non-Cacheable Region #2
59-58 MA Map Type
1-0
3-2
5-4
7-6
5A
5B
5C
5D
5E
6A
6B
6C
6D
50
51
52
53
5F
60
61
62
63
64
65
66
67
68
69
A
B
C
D
E
F
8
9
7HFKQRORJLHV ,QF
Vendor ID
Device ID
Command
Status
Revision ID
Program Interface
Sub Class Code
Base Class Code
-reserved- (cache line size)
Latency Timer
Header Type
Built In Self Test (BIST)
Request Phase Control
Response Phase Control
Dynamic Defer Timer
Miscellaneous
DRAM Type
ROM Shadow Control C0000-CFFFF
ROM Shadow Control D0000-DFFFF
ROM Shadow Control E0000-FFFFF
DRAM Timing for Banks 0,1
DRAM Timing for Banks 2,3
DRAM Timing for Banks 4,5
-reserved- (unassigned)
DRAM Control
DRAM Clock Select
DRAM Refresh Counter
DRAM Arbitration Control
SDRAM Control
DRAM Control Drive Strength
:H &
:H &R R QQHFW
Bank 0 Ending (HA[29:22])
Bank 1 Ending (HA[29:22])
Bank 2 Ending (HA[29:22])
Bank 3 Ending (HA[29:22])
Bank 4 Ending (HA[29:22])
Bank 5 Ending (HA[29:22])
QQHFW
0000 00A0 RO
0000 0008 RW
Default Acc
Default Acc
Default Acc
1106
0601
0006
0290
0000
0000
0000
0000
0000
EC
EC
EC
nn
00
00
06
00
00
00
00
00
00
00
00
00
00
00
00
10
00
01
01
01
01
01
01
00
00
00
00
00
00
00
00
01
00
00
00
RW
WC
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
—
—
—
—
—
—
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-24-
Device-Specific Configuration Registers (continued)
AB-A8 AGP Command
AC-EF -reserved- (unassigned)
7B-7D -reserved-
A7-A4 AGP Status
Offset PCI Bus Control
Offset GART/TLB Control
Offset AGP Control
Offset BIOS Scratch
Offset Miscellaneous Control
Offset Back Door Control
8B-88 Gr. Aperture Translation Table Base
8C-8F -reserved- (unassigned)
FF-FE Back Door Device ID
7E-7F DLL Test Mode (do not program)
80-FF -reserved-
F0-F7 BIOS Scratch
83-80 GART/TLB Control
85-87 -reserved- (unassigned)
AC
AD
7A
A0
A1
A2
A3
FA
FB
FC
FD
70
71
72
73
74
75
76
77
78
79
84
F8
F9
PCI Buffer Control
CPU to PCI Flow Control 1
CPU to PCI Flow Control 2
PCI Master Control 1
PCI Master Control 2
PCI Arbitration 1
PCI Arbitration 2
Chip Test (do not program)
PMU Control 1
PMU Control 2
Miscellaneous Control
Graphics Aperture Size
AGP ID
AGP Next Item Pointer
AGP Specification Revision
-reserved- (unassigned)
AGP Control
AGP Latency
DRAM Arbitration Timer 1
DRAM Arbitration Timer 9
CPU Direct Access FB Base Address
Frame Buffer Conrol
Back Door Control 1
Back Door Control 2
VT8601 Apollo ProMedia
Register Summary Tables
0000 0000 RW
0000 0000 RW
0000 0000 RW
0700 0203 RO
0000 0000 RW
Default Acc
Default Acc
Default Acc
Default Acc
Default Acc
Default Acc
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
02
00
10
00
00
00
00
00
00
00
00
00
00
00
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
—
—
—
—
—
—