VT8601 Via, VT8601 Datasheet - Page 84

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Graphics Signature Analyzer Registers
SR21 – Signature Control ................................................. RW
SR23-22 – Signature Data ................................................. RO
Graphics Power Management Control Registers
SR24 – Power Management Control ............................... RW
Revision 1.3 September 8, 1999
15-0 Signature Data
5-0
5-4
7
6
7
6
3
2
1
0
7HFKQRORJLHV ,QF
Signature Generator Enable
Signature Source Select
Bit Select
RAMDAC Clock During RAMDAC Powerdown
Enable VCLK2 VCO Directly
(without warmup sequence)
Clock Input Divisor
Divisor for 14.318 MHz clock input to MCLK to
drive DRAM refresh cycles in power managed
modes.
Power Management Slow MCLK
Enable MCLK VCO Directly
(without warmup sequence)
Enable MCLK VCO Directly
(without warmup sequence)
DAC Power
:H &
:H &R R QQHFW
00 1
01 2
10 4
11 8
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Disable (readback 0 indicates done).......default
Enable (readback 1 indicates busy)
TV / CRT ...............................................default
LCD
14.318 MHz ..........................................default
14.31818 MHz divided by 2
Enable
Don’t Enable ..........................................default
Use divided MCLK during standby & suspend
Use MCLK during standby & suspend........ def
Enable
Don’t Enable .........................................default
Enable
Don’t Enable .........................................default
Off
On
.....................................................default
.............................................. default = 0
.....................................................default
-78
Graphics Connector Control Registers
SR25 – Monitor Sense ....................................................... RO
SR37 – Video Key Mode .................................................. RW
SR38 – Advanced Feature Connector (AFC) Control ... RW
7-3
2-0
5-4
3-0
2-1
7
6
7
6
5
4
3
0
Reserved
Monitor Sense Result: [red, green, blue]
Feature Connector Input Clock Polarity
Signal Output (AFC Processing)
Feature Connector Input Pixel Clock Tuning
Overlay Key Type
Reserved
DCLK Rate (set after other bits for syncronization)
DCLK Phase Select (if bit-6 = 1)
DCLK Output Polarity
VCLK Input Polarity
Reserved
Pixel Data Bus Output Enable Control
0000 VGA Port Only...................................... default
0001 Color Key & Video Key
0010 Color Key & not Video Key
0011 Color Key
0100 Not Color Key & Video Key
0101 Video Key
0110 Color Key XOR Video Key
0111 Color Key | Video Key
1000 Not Color Key & Not Video Key
1001 Color Key XNOR Video Key
1010 Not Video Key
1011 Color Key | Not Video Key
1100 Not Color Key
1101 Not Color Key | Video Key
1110 Not Color Key | Not Video Key
1111 Video Port Only
00 0 ns
01 4 ns
10 8 ns
11 12 ns delay of pixel clock with respect to data
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal................................................... default
Inverted
Signal output is sent before AFC processingdef
Signal output is sent after AFC processing
PCLK .................................................... default
PCLK / 2
180 degree phase shift ........................... default
In phase
Normal when bit-6 = 0........................... default
Inverted
Normal................................................... default
Inverted
Disable Output Drive............................. default
Disable drive only when EVIDEO# is low
........................................ always reads 0
.................................................... default
........................................ always reads 0
........................................ always reads 0
VT8601 Apollo ProMedia
VGA Extended Registers