M12L16161A-4.3T ETC, M12L16161A-4.3T Datasheet - Page 26

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M12L16161A-4.3T

Manufacturer Part Number
M12L16161A-4.3T
Description
512K x 16Bit x 2Banks Synchronous DRAM
Manufacturer
ETC
Datasheet

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C L O C K
A D D R
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
Elite Semiconductor Memory Technology Inc.
C K E
C A S
R A S
D Q M
W E
DQ
C S
MODE REGISTER SET CYCLE
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
Mode Register Set Cycle
0
1
M R S
Key
* N o t e 3
* N o t e 2
* N o t e 1
2
H I G H
H i - Z
N e w C o m m a n d
3
R a
4
5
6
Auto Refresh Cycle
0
A u t o R e f r e s h
1
P.26
2
H I G H
H i - Z
3
4
t
R F C
5
Publication Date : Jan. 2000
6
7
M12L16161A
8
Revision : 1.3u
N e w C o m m a n d
: D o n ' t C a r e
9
1 0

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