HY5PS1G421LM HYNIX [Hynix Semiconductor], HY5PS1G421LM Datasheet - Page 35

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HY5PS1G421LM

Manufacturer Part Number
HY5PS1G421LM
Description
1Gb DDR2 SDRAM(DDP)
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
Rev. 0.2 / Oct. 2005
Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4
operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated
CK/CK
CMD
DQS/
DQS
DQ’s
Post CAS
T0
Write A
T1
NOP
WL = RL - 1 = 4
Post CAS
T2
Write B
T3
NOP
DQS
DQS
T4
DIN A
NOP
0
DIN A
1
T5
DIN A
NOP
2
DIN A
3
T6
DIN B
NOP
0
1HY5PS12421(L)M
DIN B
HY5PS12821(L)M
1
T7
DIN B
NOP
2
DIN B
3
T8
NOP
35

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