PDM31096SA10SO ETC1 [List of Unclassifed Manufacturers], PDM31096SA10SO Datasheet

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PDM31096SA10SO

Manufacturer Part Number
PDM31096SA10SO
Description
4 Megabit 3.3V Static RAM 512K x 8-Bit
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
Features
n
n
n
n
n
Functional Block Diagram
Rev. 2.4 - 5/27/98
High-speed access times
Com’l: 8, 10, 12, 15, and 20 ns
Ind’l.: 12, 15 and 20 ns
Low power operation
- PDM31096SA
Single +3.3V ( 0.3V) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Active: 300 mA (Max)
Standby: 25mW
CE
WE
OE
Addresses
I/O
I/O
0
7
A
A
18
0
PRELIMINARY
Decoder
Input
Data
Control
Description
The PDM31096 is a high-performance CMOS static
RAM organized as 524,288 x 8 bits. Writing is
accomplished when the write enable (WE) and chip
enable CE inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and
OE are both LOW.
The PDM31096 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31096 is available in a 36-pin 400-mil plas-
tic SOJ package and a 44-pin plastic TSOP (II)
package.
Column I/O
Memory
Matrix
• • • • •
4 Megabit 3.3V Static RAM
PDM31096
512K x 8-Bit
1
10
11
12
1
2
3
4
5
6
7
8
9

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PDM31096SA10SO Summary of contents

Page 1

Features High-speed access times n Com’l: 8, 10, 12, 15, and 20 ns Ind’l.: 12, 15 and 20 ns Low power operation n - PDM31096SA Active: 300 mA (Max) Standby: 25mW Single +3.3V ( 0.3V) power supply n TTL-compatible inputs ...

Page 2

Pin Configuration TSOP (II I/OO 36 I/O7 9 ...

Page 3

DC Electrical Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH NOTE:1.V (min) = –3.0V for ...

Page 4

Recommended DC Operating Conditions Symbol Parameter V Supply Voltage CC V Supply Voltage SS Industrial Ambient Temperature Commercial Ambient Temperature AC Test Conditions Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load ...

Page 5

Read Cycle No. 1 ADDR D OUT ( Read Cycle No. 2 ADDR OUT AC Electrical Characteristics Description READ Cycle READ cycle time Address access time Chip enable access time Output hold from ...

Page 6

Write Cycle No. 1 (Write Enable Controlled) ADDR OUT Write Cycle No. 2 (Write Enable Controlled) ADDR OUT NOTE: Output Enable (OE) is inactive (high) 6 PRELIMINARY ...

Page 7

Write Cycle No. 3 (Chip Enable Controlled) ADDR OUT NOTE: Output Enable (OE) is inactive (high) AC Electrical Characteristics Description WRITE Cycle WRITE cycle time Chip enable to end of write Address valid to end ...

Page 8

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