EM65101AF EMC [ELAN Microelectronics Corp], EM65101AF Datasheet - Page 27

• Manufacturer Part Number: EM65101AF
• Description: 128COM/160SEG 16 Gray Scale Level LCD Driver
• Manufacturer: EMC [ELAN Microelectronics Corp]

Product Specification (V0.4) 08.15.2005
(This specification is subject to change without further notice)
7.6 Display Timing Circuit
The display timing circuit generates internal signals and timing pulses (internal LP,
FLM, and M) by the clock.
7.6.1 Signal Generation for the Display Line Counter and the
Clock frequencies are generated to the line counter and the display data latching circuit
from the display clock (internal LP). Synchronized with the display clock (internal LP),
the line addresses of Display RAM are generated and the 160-segement bits display
data are latched to display data latching circuit to output to the LCD drive circuit
(Segment outputs)
independent of MPU
accesses the display data.
7.6.2 Generation of the Alternate Signal M (Internal) and the
LCD alternate signal M (internal) and synchronous signal FLM (internal) are generated
by the display clock LP (internal)
LCD drive circuit. Normally, FLM generates alternate drive waveform every frame
(M-signal level is reversed every single frame). However, by setting up data in an n-line
reverse register and n-line alternate control bit (NLIN), an n-line reverse waveform is
generated at “1.” These control bits are NLIN and EOR.
When NLIN = “H” :
EOR=0
EOR=1
7.6.3 Display Data Latching Circuit
Display data latching Circuit temporally latches display data that outputs display data to
the LCD driver circuit from display RAM every one common period. Normal
display/reverse display, display ON/OFF, and display all on functions are operated by
controlling data in the display data latch. Therefore, no data within display RAM
changes.
LP (internal)
FLM (internal)
M (internal)
Symbol
Display Data Latching Circuit
Synchronous Signal FLM (Internal)
M always reverses on the nth raster row regardless of whether the end of a
frame is reached.
M reverses at the nth raster row and restarts the raster row count at the start
of every frame.
.
The LP is a latch clock signal.
At the raising edge, count the display line counter. At the falling edge,
output the LCD drive signal.
The signal for the LCD display synchronous signals.
When FLM is set to “H,” the display start-line address is present.
The signal for alternate signals of LCD drive output
Display data read out of to the LCD drive circuit is completely
.
Thus, MPU has no relationship to the read-out operation which
.
128COM/160SEG 16 Gray Scale Level LCD Driver
FLM generates alternated drive waveform to the
Description
EM65101
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