EM25LV010-25KGBS EMC [ELAN Microelectronics Corp], EM25LV010-25KGBS Datasheet
EM25LV010-25KGBS
Related parts for EM25LV010-25KGBS
EM25LV010-25KGBS Summary of contents
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... General Description The EM25LV010 bits Flash memory organized as 128K x 8 bits and uses a single voltage of 2.7-3.6V for Program and Erase. It features a typical 2ms Page-Program time and a typical 40ms Block-Erase time. The device uses status register to detect the completion of the Program or Erase operation. To protect against inadvertent write, the device has on-chip hardware and software data protection schemes ...
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... Top View VSS 5 Figure 0: Pin Assignments Pin Name Function C Serial Clock D Serial Data Input Q Serial Data Output S# Chip Select W# Write Protect 6 Hold# Hold V Supply Voltage DD V Ground SS Table 1: Pin Description EM25LV010 SPECIFICATION VCC HOLD Page ...
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... The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPI Mem ory Mem ory Device Device HOLD# Figure 2: SPI Modes Supported EM25LV010 SPECIFICATION SPI SPI Mem ory Device HOLD MSB ...
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... I/O Buffer and Data Latches 256 Byte Data Buffer Block3 18000h Block2 10000h Block1 08000h Block0 00000h 256 Bytes (Page Size) Y-Decoder Figure 2: SPI Modes Supported EM25LV010 SPECIFICATION 1FFFFh 17FFFh 0FFFFh 07FFFh Status Register 1FFFFh Size of the read-only m em ory area 000FFh ...
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... Status Register (SRWD, BP1, and BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... Write Enable Latch Bit Table 3: Status Register Format Memory Contents Protected Area None Upper quarter (Block 3) Upper half (2 blocks: 2 and 3) All blocks (4 blocks & 3) Table 4: Protected Area Sizes EM25LV010 SPECIFICATION b0 BUSY Bit Unprotected Area * All blocks (4 blocks & 3) Lower three-quarters (3 blocks ...
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... Write Protect (W#) (see Table 6). Hold Function The Hold (HOLD#) signal allows the EM25LV010 operation to be paused while it is actively selected with S# at low. To enter into the Hold condition, the device must be selected with Chip Select (S#) at Low. However, setting this Hold signal Low does not terminate any Write Status Register, Program, or Erase cycle that is currently in progress ...
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... High, and then drive Chip Select (S#) to Low. This prevents the device from going back to the Hold condition. Write Protect The EM25LV010 offers the following data protection mechanism features to prevent inadvertent write from noisy environment: Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification ...
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... Write Protection of the Status Register Protected against Page Program, Block Erase and Chip Erase. Protected against Page Program, Block Erase and Chip Erase. Table 6: Protection Modes EM25LV010 SPECIFICATION Memory Content 1 Protected Area Unprotected Area Ready to accept Page Program, and Block Erase instructions. ...
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... One-byte Instruction Code 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 1010 1011 1001 0000 Table 7: Instruction Set EM25LV010 Address Dummy Data Bytes Bytes Bytes ∞ ...
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... Register. Before it is accepted, a Write Enable (WREN) instruction must be executed first. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... Chip Select (S#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction executed while a Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... Chip Select (S#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction will not execute. This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... The Chip Erase (CE) instruction is entered by driving the Chip Select (S#) Low, followed by the instruction code on Serial Data Input (D). The Chip Select (S#) must be driven Low for the entire duration of the sequence. This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... ICC2 and the Deep Power-Down mode is entered. Any Deep Power-Down (DP) instruction executed while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory SPECIFICATION EM25LV010 Page ...
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... Deep Power-Down (RES) and Read Device ID instruction is not decoded and has no effect on the cycle that is in progress. The device features an 8-bit Device ID (value for the EM25LV010 is 10h). This can be read using the Release from Deep Power-Down (RES) and Read Device ID instruction. ...
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... V threshold. However, the device may CC WI remains below V (min) at such time. No Write Status Register threshold WI has risen above V CC delay has not yet fully elapsed. PUW EM25LV010 SPECIFICATION is less CC has PUW (min), the device can be selected CC Page ...
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... Program, Erase and Write Commands are Rejected by the Device t PUW t VSL Figure 4: Power-up Timing Parameter Write Inhibit Voltage V (min low CC Time Delay to Write Instruction WI EM25LV010 SPECIFICATION Device Fully Read Access Allowed Accessible Min Max Threshold Voltage Page ...
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... This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory Parameter 1 2 Ω Ω , R2=500 ) Table 9: Absolute Maximum Ratings Parameter Table 10: Operating Conditions Parameter Table 11: AC Measurement Conditions EM25LV010 SPECIFICATION Min Max Unit °C -65 150 °C 235 -0.6 4.0 V -0.6 4 ...
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... Table 10) S#= S#= C=0 Q=open S#=V CC S#=V CC S#=V CC S#= =1.6mA OL I =-100µA OH Table 13: DC Characteristics EM25LV010 SPECIFICATION 0.7V CC 0.3V CC Min Max 8 6 Min Max ±2 ± 25MHz -0.5 0.3 V 0. 0.4 V -0.2 CC ...
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... S# High to Standby Mode without Electronic Signature Read S# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Page Program Cycle Time Block Erase Cycle Time Chip Erase Cycle Time Table 14: AC Characteristics EM25LV010 SPECIFICATION Min Type Max Unit D.C. 33 MHZ D ...
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... This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory t SLCH t CHDX Figure 6: Serial Input Timing Figure 7: Hold Timing Figure 8: Output Timing EM25LV010 SPECIFICATION t SHSL t SHCH t CHSH t CHCL t CLCH LSB ...
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... Figure 11: Write Disable (WRDI) Sequence This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory Hold Condition Hold Condition Figure 9: Hold Condition Activation Instruction High Impedance Ins truction H igh Im pedance EM25LV010 SPECIFICATION 7 7 Page ...
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... Instruction Satus Register MSB 24-Bit Address MSB 7 MSB EM25LV010 SPECIFICATION Status Register Out MSB Data Out 1 Data Out ...
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... Address MSB Data Byte MSB Figure 16. Page Program (PP) Sequence EM25LV010 SPECIFICATION 31 0 Data Out MSB Data Byte MSB ...
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... Instruction Figure 19: Deep Power-Dow-n Sequence Dummy Bytes MSB 7 MSB Deep Power-down Mode EM25LV010 SPECIFICATION Stand-by Mode Deep Power-down Mode t RES2 Device Stand-by Mode ...
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... Deep Power-down Mode 24-Bit Address MSB Manufacturer ID (1Fh) MSB EM25LV010 SPECIFICATION t RES1 Stand-by Mode Manufacturer ID (7Fh) MSB ...
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... Appendix ORDERING INFORMATION (Standard Products) The order number is defined by a combination of the following elements. EM25LV010 -33 M This specification is subject to change without further notice. (11.08.2004 V1.0) 1 Megabit (128K x 8) Serial Flash Memory S Description (Lead) free package Package Type M = SO8 (150mm) KGB = Known Good Dice (for wafer dice sell) ...
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... Shenzhen, Ltd. Shanghai Corporation, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. 23/Bldg. #115 Lane 572, Bibo Road Shenzhen Hi-Tech Industrial Park Zhangjiang Hi-Tech Park Shenzhen, Guandong, CHINA Shanghai, CHINA Tel: +86 755 2601-0565 Tel: +86 021 5080-3866 Fax: +86 755 2601-0500 Fax: +86 021 5080-4600 EM25LV010 Page ...