EM25LV010-25KGBS EMC [ELAN Microelectronics Corp], EM25LV010-25KGBS Datasheet - Page 17

• Manufacturer Part Number: EM25LV010-25KGBS
• Description: 1 Megabit (128K x 8) Serial Flash Memory
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
Release from Deep Power-Down (RES) and Read Device ID
Once the device has entered the Deep Power-Down mode, all instructions are ignored except
the Release from Deep Power-Down (RES) and Read Device ID instruction. Executing this
instruction will take the device out of the Deep Power-Down mode. The instruction can also
be used to read the 8-bit Device ID of the device on Serial Data Output (Q).
The Release from Deep Power-Down (RES) and Read Device ID instruction always provides
access to the Device ID of the device, and can be applied even if the Deep Power-Down mode
has not been entered, except when an Erase, Program, or Write Status Register cycle is in
progress,
While an Erase, Program or Write Status Register cycle is in progress, any Release from
Deep Power-Down (RES) and Read Device ID instruction is not decoded and has no effect on
the cycle that is in progress.
The device features an 8-bit Device ID (value for the EM25LV010 is 10h). This can be read
using the Release from Deep Power-Down (RES) and Read Device ID instruction.
The device is first selected by driving Chip Select (S#) Low. The instruction code is followed
by 3 dummy bytes with each bit being latched in on Serial Data Input (D) during the rising edge
of Serial Clock (C). Then, the 8-bit Device ID, stored in the memory, is shifted out on Serial
Data Output (Q) with each bit being shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 20. The Release from Deep Power-Down (RES)
and Read Device ID instruction is terminated by driving Chip Select (S#) High after the Device
ID has been read at least once. Sending additional clock cycles on Serial Clock (C), while
Chip Select (S#) is driven Low, causes the Device ID to be output repeatedly.
When Chip Select (S#) is driven High, the device is put in the Standby mode. If the device
was previously in the Deep Power-Down mode, the transition to the Standby mode is delayed
by tRES2. Chip Select (S#) must remain High for at least tRES2(max) as specified in Table
14. Once in the Standby mode, the device waits to be selected so that it can receive, decode,
and execute instructions. Driving Chip Select (S#) High after the 8-bit instruction byte is
received by the device, but before the whole of the 8-bit Device ID is transmitted for the first
time (as shown in Figure 21), still insures that the device is taken out of the Deep Power-Down
mode. It however, incurs a delay (tRES1) before the device is put in Standby mode. Chip
Select (S#) must remain High for at least tRES1(max), as specified in Table 14. Once in the
Standby mode, the device waits to be selected so that it can receive, decode, and execute
instructions.
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This specification is subject to change without further notice. (11.08.2004 V1.0)