EM65567AF EMC [ELAN Microelectronics Corp], EM65567AF Datasheet - Page 33

• Manufacturer Part Number: EM65567AF
• Description: 66 COM/ 96 SEG 256 Color STN LCD Driver
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM65567
66 COM/ 96 SEG 256 Color STN LCD Driver
7.14 Display Timing Circuit
The display timing circuit generates internal signals and timing pulses (LP, FLM, M and CLK) by clock. It can select external
input (CK) or internal oscillation.
By setting up Master/Slave mode (M/S), the state of timing pulse pins and the timing generator changes.
M/S Pin
Mode LP Pin M Pin FLM Pin CLK Pin
State of timing generator
L
Slave
Input Input
Input
Input
LP,FLM,M generation stop
H
Master Output Output Output Output
Operation state
Display timing pulse pins and Generator State
7.15 Signal Generation to Display Line Counter, and Display Data Latching Circuit
Both the clock to the line counter and clock to display data latching circuit from the display clock (LP) are generated.
Synchronized with the display clock (LP), the line addresses of Display RAM are generated and 288-bits display data are
latched to display data latching circuit to output to the LCD drive circuit (Segment outputs). Read-out of the display data to
the LCD drive circuit is completely independent of MPU. Therefore, MPU that has no relationship the read-out operation of
the display data can access.
7.16 Generation of the Alternated Signal (M) and the Synchronous Signal (FLM)
LCD alternated signal (M) and synchronous signal (FLM) are generated by the display clock (LP). The FLM generates
alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame
(M-signal level is reversed every one frame). However, by setting up data (n-1) in an n-line reverse register and n-line
alternated control bit (NLIN) at “1”, n-line reverse waveform is generated. When the EM65567 is used in multi chip system,
master chip must provide LP, FLM, and M signals for the slave chip.
7.17 Display Data Latching Circuit
Display data latching Circuit temporally latches display data that is output display data to LCD driver circuit from display
RAM every one common period. Normal display/reverse display, display ON/OFF, and display all on functions are operated
by controlling data in display data latch. Therefore, no data within display RAM changes.
7.18 Output Timing of LCD Driver
Display timing at Normal mode (not reverse mode), 1/66 DUTY, and on monochrome mode.
* This specification is subject to be changed without notice.
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2003/1/9 (V0.1)